Moves the MTRR setup for graphics memory (GMADR) from the
`soc_load_logo_by_coreboot()` function to `do_silicon_init()`. This
refactors the logic into a new helper function,
`soc_mark_gfx_memory()`, which acquires a temporary Write-Combine
(WC) MTRR.
The MTRR is now configured earlier in the silicon initialization
process, making the setup and cleanup independent of the
`soc_load_logo_by_coreboot()` function itself.
This improves FSP-S performance and ensures the MTRR is correctly
managed within the silicon initialization flow which was earlier
missed when platform selects `USE_COREBOOT_FOR_BMP_RENDERING` aka
rendering the BMP logo using coreboot driver and not using FSP driver
logic.
The cleanup of the MTRR is also moved to `do_silicon_init()` to pair
with the earlier setup.
TEST=Successfully boot to OS on google/fatcat using coreboot for logo
rendering.
w/o this patch
```
963:returning from FspMultiPhaseSiInit 1,164,839 (123,244)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,143,974 (115,443)
```
Change-Id: I5da3178c622f5fd6cb3d7f3f574e59f9ed5a5b3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88982
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5f0225a7b5