mb/siemens/mc_rpl1: Enable 4 P-Cores, disable E-Cores

Set the active core configuration for the processor on this variant to
use 4 P-cores and 0 E-cores. This ensures that only the performance
cores are enabled, which matches the intended use case for this specific
board variant.

Change-Id: If79b13fea16bcd369feb438aab4ab11dd63d4fab
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88958
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/mc_rpl/include/baseboard/variants.h

@@ -34,6 +34,7 @@ void variant_configure_early_gpio_pads(void);
 size_t variant_memory_sku(void);
 const struct mb_cfg *variant_memory_params(void);
 void rpl_memory_params(FSPM_UPD *memupd);
+void variant_configure_fspm(FSPM_UPD *memupd);
 
 /* Modify devictree settings during ramstage */
 void variant_devtree_update(void);

src/mainboard/siemens/mc_rpl/romstage_fsp_params.c

@@ -61,4 +61,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
 		configure_external_clksrc(m_cfg);
+
+	variant_configure_fspm(memupd);
 }

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk

@@ -2,3 +2,4 @@
 
 bootblock-y += early_gpio.c
 ramstage-y += gpio.c
+romstage-y += variant.c

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/variant.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <baseboard/variants.h>
+
+void variant_configure_fspm(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+
+	m_cfg->ActiveCoreCount = 4;
+	m_cfg->ActiveSmallCoreCount = 0;
+}