1. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka.
2. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka.
3. Set TPM I2C bus to 0x01 for francka.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85115
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it
route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1
is also being programmed to GPP_B which makes the overall configuration
invalid.
The fix is to program the GPE0_DW0 route to a GPIO group which is not
already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A.
Additionally, the common GPE route configuration is moved to baseboard.
BUG=b:378455259
TEST=Verify wake from S0ix when charger is connected
Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds an assertion to ensure that the values of
pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the
soc_intel_<soc>_config structure are unique.
This check helps to catch potential configuration errors early on,
preventing unexpected behavior during system initialization.
TEST=Built and booted normally. No assertion failure observed.
Able to catch the hidden issue due to overlapping Tier 1 GPE
configuration.
[DEBUG] CPU: Intel(R) Core(TM) 3 N355
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a
[DEBUG] CPU: AES supported, TXT supported, VT supported
...
...
[DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c',
line 163
Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The lower_basic_mem_test_size SoC setting (LowerBasicMemTestSize UPD)
request FSP-M to reduce the size of memory tested after memory
training. This option reduces the boot time. This is considered a safe
option to enable on a well validated board.
BUG=b:357011633
TEST=LowerBasicMemTestSize UPD is set when lower_basic_mem_test_size
is set
Change-Id: I465e9c138ac8f2079bfd506add4667201a8fa533
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85130
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Limit the ACPI OpRegion to cover only MBOX3. This seems to fix
BSOD errors seen on Windows 10/11 as reported at [1].
1: https://ticket.coreboot.org/issues/327
Change-Id: Ia2affa799e5cd84c0a03330e0f78919755f0e8ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81295
Reviewed-by: Joel Linn <jl_coreboot@conductive.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add a helper function to identify PCI IOAPICs.
Will be used in the following commits.
Change-Id: Ibe50934260b025575440fd52eace73fe2327a193
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Update microcode on BSP before MPinit and on all APs if necessary.
When the APs already have a MCU loaded, MPinit will skip the update.
This aligns the code with other platforms that attempt to update the
microcode in MPinit even when FIT already has loaded a MCU.
Drop the UPD PcdCpuMicrocodePatchBase to prevent FSP-S from updating
MCU before MPinit runs.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I7df6f82055a879a738fd29092e750084557bbd5c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84848
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use Kconfig symbol CPU_BCLK_MHZ as done on CPX.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I8a0a51d4280e4370e0e8695f8b9d8f2ed943d9e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Since SKX and CPX are using the PCH, copy the code from CPX and
lock the PMC in the same place.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I9495456fc2650b25ba164b336dc10ea0b88989aa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84846
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use get_platform_thread_count() instead of duplicated
get_thread_count(), that is also less precise.
Change-Id: I70c095c284aab6898b8351e82243f534963f333b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84845
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lock all PCU registers on all sockets. The same code can be found
on CPX, which is basically the same CPU. Once the differences between
CPX and SKX are minimal, the platforms can be merged into one codebase.
Change-Id: I73eaa0905e8a418fc9dfe515c42cd257c041cf61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84843
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fn key on telith emits a scancode of 94 (0x5e).
BUG=b:372506691
TEST=Flash telith, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment2
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate different hardware configurations.
Specifically, GPP_E07 is not connected (NC) on google/fatcat boards
with the Microchip EC AIC. However, it is required for google/fatcat
boards with Nuvoton/ITE AICs.
BUG=b:378603337
Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85106
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current WWAN(LTE) does not require any sar setting from RF team's
suggestion, and sar sensor will be removed from DVT schematic.
To reserve the extendibility, add the fw_config DB_1A_LTE_SAR:
field DB_USB 11 12
option DB_1A 0 (None LTE)
option DB_1A_LTE 1 (LTE without sar sensor)
option DB_1A_LTE_SAR 2 (LTE with sar sensor)
end
Base on the fw_config to enable/disable related functions:
0)Disable WWAN and Sar if DB_USB = DB_1A
1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE
2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR
BUG=b:375341992
TEST=Build and verify on jubilant by DB_USB= 0,1,and 2 of fw_config
Check sar sensor and WWAN module from commands:
ls -l /sys/bus/i2c/devices
i2cdetect -y -r
lsusb
Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85107
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be
reused for multiple domains.
Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This will ensure that the user is informed about an ongoing CSE FW Sync.
BUG=b:378458829
TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed
during CSE FW Sync.
Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Definitions of __fls/__ffs from lib.h and fms/fls from
cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is
more generic.
Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a new config option to indicate that a board has Google Strauss
keyboard. The scan code for Fn key will be set to 94 if the new config
is selected.
Previously each board was setting the integer config option for Fn key
scan code which was not scalable. The new option is a bool and can be
easily selected by different boards.
BUG=none
TEST=Verify coreboot.config before and after this change.
Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for the ALC721 codec in the device tree
and enables it based on the fw_config.
BUG=b:368495490
TEST=Boot on google fatcat board
Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch updates the eSOL rendering logic to use the
SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of
SOC_INTEL_CSE_LITE_SKU.
The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to
determine whether to render eSOL during ramstage.
The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically
indicates whether CSE synchronization is performed during ramstage,
making it a more appropriate choice for this purpose.
This change ensures that eSOL is rendered correctly during ramstage on
platforms that require CSE synchronization.
TEST=Able to render eSOL during ramstage for google/trulo.
Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out on the serial
console for bus hanging analysis.
TEST=build pass, and check log with:
[INFO ] ******************* MT8196 lastbus ******************
[INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 ---
[INFO ] 00402504
[INFO ] c34b00d6
[INFO ] 61804050
[INFO ] 00051840
[INFO ] 10401610
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
1. Add Google Ti50 TPM support
2. Configure I2C speed to I2C_SPEED_FAST_PLUS
3. Pass GPIO_GSC_AP_INT_ODL to the payload
4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now
BUG=b:317009620
TEST=build pass, boot ok and there is no CR50 TPM timeout log
Pass log:
[INFO ] Probing TPM I2C: done! DID_VID 0x504a6666
[DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a)
Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support for MT8196 DRAM calibration. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h. As MT8196's
dramc_param struct size is different from other MediaTek SoCs,
replace the hardcoded RW_MRC_CACHE size in common code with a constant
derived from chromeos.fmd.
The common emi.c can be reused for MT8196 as well, so remove the
duplicate mt8196/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
Test=Build pass
BUG=b:317009620
Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will
enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the
FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is
larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge
RW_MRC_CACHE from 8K to 16K.
TEST=Build pass
BUG=b:317009620
Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info
from the SFDP table.
TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct
has the expected entries (RPMC available, OP2 extended status as polling
method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
JESD216F.02 and JESD260 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85008
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add basic support for the Serial Flash Discoverable Parameters (SFDP)
standard which can be used to discover the parameters to interact with
any SPI flash chip that supports this mechanism. This commit adds
functionality to find specific SFDP parameter headers and print all SFDP
parameter headers, but not to parse any SFDP parameter table. This is a
preparation for a follow-up patch that adds support to parse the RPMC
SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in
the next patch, it's marked as static inline in this commit so that the
code still build; the 'inline' keyword will be removed again in that
follow-up patch.
For now, only the legacy access protocol using single bit SPI transfers
is supported, but this should cover most of the SPI NOR flash chips. In
any other case, the code will error out. It's also assumed that the SFDP
data blocks read from the SPI flash chip are small enough to fit into
the SPI host controller buffer and don't need to be broken up into
multiple transfers. This limitation will be addressed in a follow-up
patch.
JESD216F.02 was used as a reference.
TEST=On a board with a W74M12JW SPI flash chip, calling
'spi_flash_print_sfdp_headers' prints this on the console output:
Manufacturer: ef
SF: Detected ef 6018 with sector size 0x1000, total 0x1000000
SF: Exiting 4-byte addressing mode
SFDP header found in SPI flash.
major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3
SFPD header with index 0:
table ID 0xff00, major rev 0x1, minor rev 0x6
table pointer 0x80, table length DWORDS 0x10
SFPD header with index 1:
table ID 0xff84, major rev 0x1, minor rev 0x0
table pointer 0xd0, table length DWORDS 0x2
SFPD header with index 2:
table ID 0xff03, major rev 0x1, minor rev 0x0
table pointer 0xf0, table length DWORDS 0x2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Fix the checkpatch error:
Macros with complex values should be enclosed in parentheses
Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
