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mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K

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Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will
enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the
FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is
larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge
RW_MRC_CACHE from 8K to 16K.

TEST=Build pass
BUG=b:317009620

Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Jarried Lin 2024-11-08 20:10:48 +08:00 • committed by Yu-Ping Wu
commit 2919a85be8
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/rauru/chromeos.fmd
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@ -28,9 +28,9 @@ FLASH@0x0 8M {
RW_FWID_A 0x100
}
RW_MISC 36K {
RW_VPD(PRESERVE) 16K # At least 8K.
RW_VPD(PRESERVE) 8K # At least 8K.
RW_NVRAM(PRESERVE) 8K
RW_MRC_CACHE(PRESERVE) 8K
RW_MRC_CACHE(PRESERVE) 16K
RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K.
}
RW_SECTION_B 1500K {