soc/intel/xeon_sp/skx: Load microcode

Update microcode on BSP before MPinit and on all APs if necessary.
When the APs already have a MCU loaded, MPinit will skip the update.

This aligns the code with other platforms that attempt to update the
microcode in MPinit even when FIT already has loaded a MCU.
Drop the UPD PcdCpuMicrocodePatchBase to prevent FSP-S from updating
MCU before MPinit runs.

Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.

Change-Id: I7df6f82055a879a738fd29092e750084557bbd5c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84848
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/skx/chip.c

@@ -113,19 +113,6 @@ static void soc_init(void *data)
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 {
-	const struct microcode *microcode_file;
-	size_t microcode_len;
-
-	microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
-
-	if ((microcode_file) && (microcode_len != 0)) {
-		/* Update CPU Microcode patch base address/size */
-		silupd->FspsConfig.PcdCpuMicrocodePatchBase =
-		       (uint32_t)microcode_file;
-		silupd->FspsConfig.PcdCpuMicrocodePatchSize =
-		       (uint32_t)microcode_len;
-	}
-
 	mainboard_silicon_init_params(silupd);
 }
 

src/soc/intel/xeon_sp/skx/cpu.c

@@ -7,6 +7,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/mp.h>
+#include <cpu/intel/microcode.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/em64t101_save_state.h>
@@ -20,7 +21,6 @@
 #include <types.h>
 #include "chip.h"
 
-
 static const config_t *chip_config = NULL;
 
 bool cpu_soc_is_in_untrusted_mode(void)
@@ -58,6 +58,23 @@ static void xeon_configure_mca(void)
 	mca_configure();
 }
 
+/*
+ * By providing a pointer to the microcode MPinit will update the MCU
+ * when necessary and skip the update if microcode already has been loaded.
+ *
+ * When FSP-S is provided with UPD PcdCpuMicrocodePatchBase it will update
+ * the microcode. Since coreboot is able to do the same, don't set the UPD
+ * and let coreboot handle microcode updates.
+ *
+ * FSP-S updates microcodes serialized, so do the same.
+ *
+ */
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+	*microcode = intel_microcode_find();
+	*parallel = 0;
+}
+
 static void xeon_sp_core_init(struct device *cpu)
 {
 	msr_t msr;
@@ -221,10 +238,6 @@ static void post_mp_init(void)
 
 /*
  * CPU initialization recipe
- *
- * Note that no microcode update is passed to the init function. CSE updates
- * the microcode on all cores before releasing them from reset. That means that
- * the BSP and all APs will come up with the same microcode revision.
  */
 static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
@@ -232,6 +245,7 @@ static const struct mp_ops mp_ops = {
 	.get_smm_info = get_smm_info,
 	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = smm_relocation_handler,
+	.get_microcode_info = get_microcode_info,
 	.post_mp_init = post_mp_init,
 };
 
@@ -239,6 +253,13 @@ void mp_init_cpus(struct bus *bus)
 {
 	FUNC_ENTER();
 
+	const void *microcode_patch = intel_microcode_find();
+
+	if (!microcode_patch)
+		printk(BIOS_ERR, "microcode not found in CBFS!\n");
+
+	intel_microcode_load_unlocked(microcode_patch);
+
 	/*
 	 * This gets used in cpu device callback. Other than cpu 0,
 	 * rest of the CPU devices do not have