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soc/mediatek/**/spi.h: Enclose complex macros in parentheses

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Fix the checkpatch error:

 Macros with complex values should be enclosed in parentheses

Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2024-11-05 17:53:55 +08:00 • committed by Yu-Ping Wu
commit 49e6be85cd
6 changed files with 12 additions and 12 deletions
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4
src/soc/mediatek/mt8173/include/soc/spi.h
View file

@ -7,8 +7,8 @@
#define SPI_BUS_NUMBER 1
#define GET_SCK_REG(x) x->spi_cfg0_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
#define GET_SCK_REG(x) ((x)->spi_cfg0_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg)
DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0)
DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8)

4
src/soc/mediatek/mt8183/include/soc/spi.h
View file

@ -7,8 +7,8 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)

4
src/soc/mediatek/mt8186/include/soc/spi.h
View file

@ -12,8 +12,8 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)

4
src/soc/mediatek/mt8188/include/soc/spi.h
View file

@ -13,8 +13,8 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cmd_reg
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)

4
src/soc/mediatek/mt8192/include/soc/spi.h
View file

@ -7,8 +7,8 @@
#define SPI_BUS_NUMBER 8
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)

4
src/soc/mediatek/mt8195/include/soc/spi.h
View file

@ -7,8 +7,8 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)