Gang Chen 3d32f915a9 soc/intel/xeon_sp: Reserve PRMRR ... PRMRR (Protected Region Memory Range Region) are not accessible as normal DRAM regions and needs to be explicitly reserved in memory map. Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2024-11-14 14:29:23 +00:00
..
acpi	acpi_gic: Add helper for platform gicc	2024-10-08 08:58:34 +00:00
arch	arch/x86: Define macros for hard-coded HPET registers	2024-11-09 10:21:25 +00:00
commonlib	mem_chip_info: Add LPDDR5 enums to mem_chip_type	2024-11-13 02:27:23 +00:00
console
cpu	soc/intel/xeon_sp: Reserve PRMRR	2024-11-14 14:29:23 +00:00
device	pci: Add method to read PME capability	2024-10-28 22:05:54 +00:00
drivers	drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data	2024-11-12 15:41:22 +00:00
ec	ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_info	2024-11-06 22:42:52 +00:00
include	soc/intel/xeon_sp: Reserve PRMRR	2024-11-14 14:29:23 +00:00
lib	tree: Fix cast an object of type 'nullptr_t' to 'uintptr_t' error	2024-10-29 01:41:41 +00:00
mainboard	vc/google: Refactor config to set Fn key scancode	2024-11-13 10:07:13 +00:00
northbridge	nb/via/cx700: Add south module devices to chipset.cb	2024-11-11 09:17:18 +00:00
sbom
security	drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAY	2024-10-14 15:26:11 +00:00
soc	soc/intel/xeon_sp: Reserve PRMRR	2024-11-14 14:29:23 +00:00
southbridge	tree: Include static.h for remaining devicetree usages	2024-11-10 19:12:22 +00:00
superio
vendorcode	vc/google: Refactor config to set Fn key scancode	2024-11-13 10:07:13 +00:00
Kconfig