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soc/intel/alderlake: Display early Sign of Life for CSE FW Sync

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This will ensure that the user is informed about an ongoing CSE FW Sync.

BUG=b:378458829
TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed
during CSE FW Sync.

Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2024-11-11 17:34:12 -07:00 • committed by Karthik Ramasubramanian
commit 618fbe0d21
2 changed files with 11 additions and 1 deletions
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7
src/soc/intel/alderlake/romstage/romstage.c
View file

@ -205,8 +205,13 @@ void mainboard_romstage_entry(void)
}
}
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake)
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
cse_fill_bp_info();
if (CONFIG(CHROMEOS_ENABLE_ESOL) &&
is_cse_fw_update_required() && !is_cse_boot_to_rw())
ux_inform_user_of_update_operation("CSE update");
cse_fw_sync();
}
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();

5
src/soc/intel/alderlake/romstage/ux.h
View file

@ -1,3 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_
#define _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_
bool ux_inform_user_of_update_operation(const char *name);
#endif /* _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ */