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mb/google/fatcat/var/francka: Add overridetree

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Add override devicetree based on schematic_20241104.

BUG=b:376245884
TEST=emerge-fatcat coreboot

Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
Ian Feng 2024-11-13 15:47:42 +08:00 • committed by Subrata Banik
commit 1565c1d108
4 changed files with 440 additions and 1 deletions
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4
src/mainboard/google/fatcat/Kconfig
View file

@ -9,6 +9,7 @@ config BOARD_GOOGLE_FATCAT_COMMON
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_WWAN_FM350GL
select DRIVERS_AUDIO_SOF
select DRIVERS_SOUNDWIRE_ALC722
select DRIVERS_SPI_ACPI
select DUMP_SMBIOS_TYPE17
@ -133,7 +134,8 @@ config MEMORY_SOLDERDOWN
config TPM_TIS_ACPI_INTERRUPT
int
default 47 # GPE0_DW1_15 (GPP_D15)
default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
# FIXME: update as per board schematics
config UART_FOR_CONSOLE

2
src/mainboard/google/fatcat/variants/francka/Makefile.mk
View file

@ -3,5 +3,7 @@
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

140
src/mainboard/google/fatcat/variants/francka/fw_config.c Normal file
View file

@ -0,0 +1,140 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <bootstate.h>
#include <console/console.h>
#include <fw_config.h>
#include <gpio.h>
#include <inttypes.h>
/* t: base table; o: override table */
#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
/* t: table */
#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
static const struct pad_config hda_enable_pads[] = {
/* HDA_BIT_CLK */
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
/* HDA_SYNC */
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
/* HDA_SDOUT */
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
/* HDA_SDIN0 */
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
/* SOC_DMIC_CLK1 */
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
/* SOC_DMIC_DATA1 */
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
/* GPP_D09: PCH_DGPU_HOLD_RST#_R */
PAD_NC(GPP_D09, NONE),
/* GPP_D16: HDA_RST# */
PAD_NC(GPP_D16, NONE),
/* GPP_S00: SNDW_3_SCL */
PAD_NC(GPP_S00, NONE),
/* GPP_S01: SNDW_3_SDA */
PAD_NC(GPP_S01, NONE),
/* GPP_S02: SOC_DMIC_CLK0 */
PAD_NC(GPP_S02, NONE),
/* GPP_S03: SOC_DMIC_DATA0 */
PAD_NC(GPP_S03, NONE),
/* GPP_S04: SNDW2_CLK */
PAD_NC(GPP_S04, NONE),
/* GPP_S05: SNDW2_DATA0 */
PAD_NC(GPP_S05, NONE),
};
/*
* WWAN: power sequence requires three stages:
* step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
* step 2: deassert FCP#
* step 3: deassert RST# first, and then PERST#.
* NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
* at much later time and time between RST# and PERSET# is guaranteed.
*/
static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
/* GPP_A09: SOC_WWAN_OFF#_SW */
PAD_CFG_GPO(GPP_A09, 0, PLTRST),
/* GPP_B20: SOC_WWAN_RST# */
PAD_CFG_GPO(GPP_B20, 0, PLTRST),
/* GPP_D03: SOC_WWAN_PCIE_RST# */
PAD_CFG_GPO(GPP_D03, 0, PLTRST),
};
static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
/* GPP_A09: SOC_WWAN_OFF#_SW */
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
};
static const struct pad_config wwan_pwr_seq3_pads[] = {
/* GPP_D03: SOC_WWAN_PCIE_RST# */
PAD_CFG_GPO(GPP_D03, 1, PLTRST),
/* GPP_B20: SOC_WWAN_RST# */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_E02: SOC_WWAN_WAKE2#_R */
PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
};
static const struct pad_config wwan_disable_pads[] = {
/* GPP_A09: SOC_WWAN_OFF#_SW */
PAD_NC(GPP_A09, NONE),
/* GPP_D03: SOC_WWAN_PCIE_RST# */
PAD_NC(GPP_D03, NONE),
/* GPP_B20: SOC_WWAN_RST# */
PAD_NC(GPP_B20, NONE),
/* GPP_A10: SOC_WWAN_RA_DIS#_SW */
PAD_NC(GPP_A10, NONE),
/* GPP_E02: SOC_WWAN_WAKE2#_R */
PAD_NC(GPP_E02, NONE),
};
static const struct pad_config bridge_disable_pads[] = {
/* GPP_D18: CLKREQ_PCIE#6 */
PAD_NC(GPP_D18, NONE),
};
void fw_config_configure_pre_mem_gpio(void)
{
if (!fw_config_is_provisioned()) {
printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
return;
}
if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT)))
GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
/*
* NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
* FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
* and FCP#) is '0'. Therefore, it will be fine even though there is no
* GPIO configured for other PADs via fw_config to have the time delay
* introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
* configured in sequence 1. Although the Tpr is '0' in the datasheet, three
* stages are preserved at this time to guarantee the sequence shown in the
* datasheet timing diagram.
*/
if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT)))
GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
}
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (!fw_config_is_provisioned()) {
printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
return;
}
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)))
GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) {
GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);
} else {
GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
}
if (fw_config_probe(FW_CONFIG(BRIDGE, BRIDGE_HAYDEN))) {
GPIO_PADBASED_OVERRIDE(padbased_table, bridge_disable_pads);
}
}

295
src/mainboard/google/fatcat/variants/francka/overridetree.cb
View file

@ -1,7 +1,302 @@
fw_config
field PDC_CONTROL 0 1
option PDC_RTS 0
option PDC_TI 1
end
field AUDIO 3 5
option AUDIO_ALC256M_CG_HDA 0
option AUDIO_ALC721_SNDW 1
option AUDIO_CS42L43_CS35L56_SNDW 2
option AUDIO_ALC722_ALC1320_SNDW 3
end
field BRIDGE 6 7
option BRIDGE_HAYDEN 0
option BRIDGE_BARLOW 1
option BRIDGE_GOTHIC 2
end
field WWAN 8
option WWAN_PRESENT 0
option WWAN_ABSENT 1
end
end
chip soc/intel/pantherlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_H"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
register "max_dram_speed_mts" = "7467"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
# Enable EDP in PortA
register "ddi_port_A_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
}"
# TCSS USB3
register "tcss_aux_ori" = "1"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C1 | TPM(TI50) Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C4 | Touchscreen, Touchpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
device ref igpu on end
device ref iaa off end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 2)"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(4, 2)"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port2 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port3 as dfp[1].typec_port
device generic 0 on end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 0""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 1)"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(4, 1)"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(5, 1)"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 0""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 1""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb3_port2 on end
end
end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
end # CNVi
# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
device ref i2c0 on end
device ref i2c1 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H11_IRQ)"
device i2c 50 on end
end
end # #I2C1
device ref i2c4 on
chip drivers/i2c/hid
register "generic.hid" = ""ILTK0001""
register "generic.desc" = ""ILITEK Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E01_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)"
register "generic.reset_delay_ms" = "200"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 41 on end
end
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)"
register "wake" = "GPE0_DW2_18"
register "detect" = "1"
device i2c 15 on end
end
end # I2C4
device ref pcie_rp2 on
probe WWAN WWAN_PRESENT
register "pcie_rp[PCIE_RP(2)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "5"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
register "use_rp_mutex" = "true"
device generic 0 alias rp2_rtd3 on end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
register "add_acpi_dma_property" = "true"
use rp2_rtd3 as rtd3dev
device generic 0 on end
end
end # WWAN
device ref pcie_rp3 on
# Enable PCH PCIE x1 slot using CLK 2
register "pcie_rp[PCIE_RP(3)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end # SD Card
device ref pcie_rp9 on
register "pcie_rp[PCIE_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
register "srcclk_pin" = "1"
device generic 0 on end
end
end # M.2 SSD
device ref smbus on end
device ref npk on end
device ref hda on
chip drivers/sof
register "spkr_tplg" = "max98360a"
register "jack_tplg" = "rt5682"
register "mic_tplg" = "_2ch_pdm0"
device generic 0 on
probe AUDIO AUDIO_ALC256M_CG_HDA
end
end
end
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
register "wake" = "GPE0_DW2_15"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)"
register "enable_delay_ms" = "3"
device spi 0 hidden end
end # FPMCU
end
end
end