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mb/google/trulo: Fix invalid GPE route configuration

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GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it
route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1
is also being programmed to GPP_B which makes the overall configuration
invalid.

The fix is to program the GPE0_DW0 route to a GPIO group which is not
already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A.

Additionally, the common GPE route configuration is moved to baseboard.

BUG=b:378455259
TEST=Verify wake from S0ix when charger is connected

Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2024-11-15 11:36:36 +00:00 • committed by Subrata Banik
commit 34f54e4e4b
3 changed files with 5 additions and 8 deletions
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5
src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
View file

@ -1,5 +1,10 @@
chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_B"
register "pmc_gpe0_dw2" = "GPP_F"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"

4
src/mainboard/google/brya/variants/orisa/overridetree.cb
View file

@ -19,10 +19,6 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_B"
register "pmc_gpe0_dw2" = "GPP_F"
# S0ix enable
register "s0ix_enable" = "true"

4
src/mainboard/google/brya/variants/trulo/overridetree.cb
View file

@ -19,10 +19,6 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_B"
register "pmc_gpe0_dw2" = "GPP_F"
# S0ix enable
register "s0ix_enable" = "true"