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mb/google/rex/var/kanix: Add USB A1 port support

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BUG=b:366291025
TEST=emerge-rex coreboot pass

Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Tyler Wang 2024-11-07 16:37:26 +08:00 • committed by Subrata Banik
commit 7eb2a9ad4f
2 changed files with 18 additions and 2 deletions
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4
src/mainboard/google/rex/variants/kanix/gpio.c
View file

@ -205,8 +205,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_E07, NONE),
/* GPP_E08 : NC net. */
PAD_NC(GPP_E08, NONE),
/* GPP_E09 : SOC_PEN_DETECT */
PAD_CFG_GPI_SCI_LOCK(GPP_E09, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
/* GPP_E09 : [] ==> USB_OC0# */
PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG),
/* GPP_E10 : [] ==> SOC_FPMCU_INT_L */
PAD_CFG_GPI_IRQ_WAKE(GPP_E10, NONE, PWROK, LEVEL, INVERT),
/* GPP_E11 : [] ==> MEM_STRAP_0 */

16
src/mainboard/google/rex/variants/kanix/overridetree.cb
View file

@ -2,10 +2,12 @@ chip soc/intel/meteorlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1
@ -288,6 +290,13 @@ chip soc/intel/meteorlake
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
@ -308,6 +317,13 @@ chip soc/intel/meteorlake
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port2 on end
end
end
end
end