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soc/intel/alderlake: Use CSE sync in ramstage config

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This patch updates the eSOL rendering logic to use the
SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of
SOC_INTEL_CSE_LITE_SKU.

The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to
determine whether to render eSOL during ramstage.

The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically
indicates whether CSE synchronization is performed during ramstage,
making it a more appropriate choice for this purpose.

This change ensures that eSOL is rendered correctly during ramstage on
platforms that require CSE synchronization.

TEST=Able to render eSOL during ramstage for google/trulo.

Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit is contained in:
Subrata Banik 2024-11-12 13:52:34 +05:30
commit 386b7ee859
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/alderlake/romstage/fsp_params.c
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@ -439,7 +439,7 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
* packed as part of the CBFS then CSE sync will be triggered. CSE sync can take
* < 1-minute hence, let's inform the end user with an on-screen text message.
*/
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
if (esol_required) {
name = "memory training and CSE update";
} else {