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mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration

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This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate different hardware configurations.

Specifically, GPP_E07 is not connected (NC) on google/fatcat boards
with the Microchip EC AIC. However, it is required for google/fatcat
boards with Nuvoton/ITE AICs.

BUG=b:378603337

Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85106
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-11-12 12:39:59 +05:30
commit c2424ee253
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/fatcat/variants/fatcat/gpio.c
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@ -210,8 +210,13 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E06: SECURE_CAM_SW */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
#if CONFIG(BOARD_GOOGLE_FATCAT)
/* GPP_E07: Not used */
PAD_NC(GPP_E07, NONE),
#else
/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
#endif
/* GPP_E08: Not used */
PAD_NC(GPP_E08, NONE),
/* GPP_E09: USB_RD_FP_CONN_12_OC0_N */