This is proven to be more reliable when resuming from S3.
Change-Id: I479493a384ae1ca880a0caf255ea832b4bb9a366
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Have two comments, then two blocks of code makes it hard to read.
Seperate them.
Change-Id: I32d6b7c389f64305e8357f52b063628cd99816d6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86196
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or
FPS UART, or disable both UART by changing the DIP switch settings. When
DIP switch is not set for ISH, ISH RX signal is disconnected, causing
ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the
impact on ISH PM. As a result, ISH console won't accept input since this
pin is not connected.
TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main
firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86005
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently after UFS is disabled, if the device is coming out of S5 sleep
state then a warm reset is triggered such that PMC samples the UFS
function disable bit and disables the UFS controller accordingly.
Sometimes during the boot flow, an additional kind of reset gets
triggered - Power cycle Reset through CMoff. Hence initiate a warm reset
when the host comes out of S5 sleep state or Power cycle Reset through
CMoff.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode an extra warm reset is
triggered such that the UFS controller is disabled.
Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86170
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Introduce an API to read the Converged Security and Management Engine
(CSME) host firmware status register to obtain the current Power
Management event and compare it with a specified input event.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS.
Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86169
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
All of the other targets support invoking the build with the full target
arch name. RISC does not. Update the script to allow riscv64-elf to
invoke the build the same way that riscv-elf does to minimize name
mangling and exceptions needed for tooling surrounding the
architecture name in paths. Leave riscv-elf in tact as an option so
we don't break anyone else.
BUG=None
TEST=./util/crossgcc/buildgcc --platform riscv64-elf
Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the printing of the missing libstdcxx path in the warning string
when the path check fails. Also resolve the use of the variable in
the conditional statement by surrounding it with quotes.
BUG=None
TEST=Build with invalid libstdcxx path
Change-Id: I195718e43ea842970f5fa986315c9e9f11395362
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86148
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace PRINT_DEBUG() macro with printram() from device/dram/common.h
for raminit debug messages.
Define a static dummy dump_pci_device() if CONFIG(DEBUG_RAM_SETUP)
is disabled. This allows removing the DUMPNORTH() macro.
dump_spd_registers() will be cleaned up separately.
TEST=Timeless binary remains unchanged.
Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This are not used or needed, so remove the configuration for them.
Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The message printed when duplicate GPE DW register values are
detected was previously logged at the INFO level. This commit
changes the log level to WARNING, as duplicate DW values indicate
a potential misconfiguration and warrant closer attention. While
the system falls back to the default GPE route (as per MISCCFG
register), this situation should be investigated to ensure correct
platform configuration.
This change ensures that developers are more clearly notified of
potential GPE routing issues.
TEST=Built and booted on a platform using PMC GPE routing. Verified
that the message is printed at the WARNING level when duplicate DW
values are present.
Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe_init` function's check for duplicate GPE DW register values
was incomplete. It only checked for duplicates between DW0 and DW1, and
DW1 and DW2, but failed to check if DW0 and DW2 were the same.
This could lead to incorrect GPE routing if DW0 and DW2 happened to have
the same value, even if DW1 was different.
This commit corrects the check to ensure that all three DW registers
(DW0, DW1, and DW2) are compared against each other. If any two
registers have the same value, a message is printed indicating that
the default GPE route will be used.
Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe0_different_values` function previously asserted if any
two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as
introduced in commit 640a41f3ee ("soc/intel: Assert if
`pmc_/gpe0_dwX` values are not unique"). This prevented platforms from
configuring GPE routing via PMC as per default register (MISCCFG) value.
This commit modifies the check to allow all DW registers to be zero.
This enables platforms that rely on MISCCFG register for
PMC-controlled GPE routing to boot without triggering the assertion.
The change was verified by testing the following scenarios:
- All DWs zero: The system boots using the default GPE route.
No assertion occurs.
- Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion
is triggered as expected.
- Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur.
TEST=Built and booted normally. No assertion failure observed.
Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86164
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mass produced boards did not support SATA, so disable it.
Change-Id: I7477b46c929a9d9e0d0351de6146112f78cece9f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are configured incorrectly, to use the WLAN WAKE GPIOs
as enable GPIOS. Correct these to use WIFI RF KILL, and disconnect
the now unused WLAN WAKE GPIOs.
Change-Id: I12797875acacc231e155ab4e427a950a3b1b9703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: If7eab6e3f6ff94054c0101b794b960626d1df92a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: I1fbb43f7081c09848dc80a6ddedfa284a8fcce44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: I9472e003b730646fea9860d9da960d7f766bdda9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Most users leave the GNA disabled, so adjust the fallback to
match this.
Change-Id: I7779781266a63c8c9f779d25ff2c692bb498c594
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
dptf_enable is a boolean, so use true false instead of 0 1.
Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86183
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Define the generic cbmem_top_chipset() in the driver code, which will
invoke a SoC-specific vendorcode openSIL call to retrieve the low
usable DRAM address.
Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Refactor to factor out and route ACPI calls through the openSIL driver
interface to separate main SoC code from vendorcode.
Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The google/fatcat board's flash layout was modified to increase the
size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB).
The RW_UNUSED region size was reduced to accommodate the increased
RW_SECTION sizes.
This change provides additional space in the RW slots to accommodate
growth in the payload (depthcharge).
TEST=Built and flashed the image. Verified that both RW_SECTION_A and
RW_SECTION_B are populated with the correct firmware components and
that the system boots successfully.
Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This moves the FPS device from GSPI0A to GSPI0 to align with the
hardware design dated Jan'25.
The FPS device was initially placed on GSPI0A, which was incorrect. This
commit rectifies the configuration by moving it to the correct GSPI0
interface.
This change ensures that the CRFP device is correctly connected and
functions as expected.
BUG=b:377595986
TEST=Able to build and boot google/fatcat.
Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86143
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EC_DASHARO_EC_FLASH_SIZE is set regardless of whether the dasharo
EC is used. Add a dependency so it is only set when needed.
Change-Id: Icce0c7a31c89cea5e7bf89770dedbf82ff56170b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Guard the Hyper-Threading option against SOC_INTEL_ALDERLAKE_PCH_N,
as the N200 processors used don't support it.
Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86166
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If S0ix is not enabled, then it should not be reported that it
is supported.
TEST=boot linux on starlabs boards, check s2idle isn't
listed under `/sys/power/mem_sleep`.
Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86133
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Set mcufw_reserved region to non-cacheable and remove cache operation in
dvfs.c.
TEST=Build pass, boot ok.
Check MMU List by CVD (Codeviser):
0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable
BUG=b:390334489
Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit adds the Panther Lake Intel Dynamic Tuning
Technology (Intel DTT) PCI Device ID to the list of supported devices
in the ACPI Common Block DTT driver.
The Panther Lake Intel DTT PCI ID is defined in document #815002,
"Panther Lake U/H Processor - External Design Specification - Volume
1".
TEST=The SSDT ACPI table includes the DPTF device definition on
fatcat board.
Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This will configure CpuCrashLogEnable regardless of Tracehub
configuration as Crashlog feature does not have a dependency
with Tracehub.
TEST=Build fatcat and check Crashlog is enabled without enabling
Tracehub.
Change-Id: I6f37e9f4a1f55ffc576af955c92d4073068eb97a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: Ibade3043489b82e5308231472dfe2c629b591661
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit b3718dee9c.
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: I5ac2ea7978fca455d39fc7663e5cb219f3f8746f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There are no resources to allocate for LDN 0, so drop it to eliminate
a spurious cbmem log error (PNP 4e.00: missing read resources).
Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently, the eDP panel has display shift issue. This issue
is caused by too short HS-trail time.
Based on hardware design ANX7625 requires more HS-trail time to
finish mipi data packet decoding before entering LP mode.
So increase HS-trail time to avoid effect of entering LP mode.
da_hs_trail value copy from "kukui/panel_anx7625.c", verified
on corsola.
BUG=b:391304679
BRANCH=corsola
TEST=Display is normal on corsola
Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86101
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Create the pujjoniru variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:386221423
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJONIRU
Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85844
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: Icbe68adc24c18b089ff1559597bfcb74aead2a60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86129
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: Iee80595e9e7d0652a723d44b11d9dc7a1c79417a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
