mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or FPS UART, or disable both UART by changing the DIP switch settings. When DIP switch is not set for ISH, ISH RX signal is disconnected, causing ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM. As a result, ISH console won't accept input since this pin is not connected. TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main firmware boots up and runs successfully. SW1317 all switches OFF to disable both FPS and ISH UART, ISH main firmware boots up and runs successfully. Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Signed-off-by: Li Feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86005 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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2 changed files with 2 additions and 4 deletions
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@ -418,8 +418,6 @@ static const struct pad_config touchpad_i2c_disable_pads[] = {
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};
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static const struct pad_config ish_disable_pads[] = {
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/* GPP_D05: NC */
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PAD_NC(GPP_D05, NONE),
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/* GPP_D06: NC */
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PAD_NC(GPP_D06, NONE),
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/* GPP_E05: NC */
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@ -429,8 +427,6 @@ static const struct pad_config ish_disable_pads[] = {
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};
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static const struct pad_config ish_enable_pads[] = {
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/* GPP_D05: ISH_UART0_RXD */
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PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
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/* GPP_D06: ISH_UART0_TXD */
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PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
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/* GPP_E05: ISH_GP_7_SNSR_HDR */
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@ -149,6 +149,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO(GPP_D03, 1, PLTRST),
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/* GPP_D04: IMGCLKOUT_0 */
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PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
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/* GPP_D05: disable ISH_UART0_RXD */
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PAD_NC(GPP_D05, NONE),
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/* GPP_D07: NC */
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PAD_NC(GPP_D07, NONE),
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/* GPP_D08: NC */
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