Commit 266041f0e6 ("console: Add compile-time fast path when only
CBMEM console is used") introduced a typo when refactoring CBMEM console
fast path code that effectively causes consoles to never get flushed.
The fact that nobody complained in 3 years shows that the flush callback
is probably not that important for most consoles in practice. Still,
it's a pretty bad bug and should be fixed.
Change-Id: Ib9b96cb744447ccba99c4186540442b542914e01
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89397
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the statistics for actual release tag.
Change-Id: I84116caa35be2df28372dd4293ad73eb13ec9dd4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Macros are generated using the hda-decoder utility.
TEST: update coreboot in ROM with this patch -> boot Ubuntu 24.04 again
-> the hda-decoder output before and after the update are the same
and the audio works.
Change-Id: I33d693a483c43a31d6dbb75a97b3ca5f5149fd69
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
coreboot 24.12, 24.08, and 4.21 have already been released, so the
"Upcoming release" text in their titles is outdated and unnecessary.
Change-Id: I19cb5585c838c64366e057ceeaf0a18e01372bfe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Configure GPP_F10, GPP_F11, GPP_F12, GPP_F13, GPP_F16, and GPP_F17
as no-connects by default. These GPIOs will be enabled in
fw_config.c if they are needed.
BUG=b:447648103
TEST='emerge-ocelot coreboot chromeos-bootimage`, flash and boot ocelot
and verify the AUDIO_ALC721_SNDW still works.
Change-Id: I7c07581e2b29bfc3e83314a065fba7d418e07c2a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit refactors the handling of CPU IDs for the Pantherlake and
Wildcat Lake series by using a single CPU ID mask instead of listing
each individual stepping. This change simplifies the code by reducing
redundancy and making it easier to manage CPU IDs.
Previously, each stepping of the Pantherlake series had its own entry,
which led to unnecessary complexity. By consolidating these into a
single entry with a mask, we improve maintainability and reduce
potential errors.
These modifications do not affect the existing functionality but
streamline the codebase for future updates and maintenance.
TEST=CPU ID c06c1 is properly identified as "Pantherlake".
Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89375
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:448253910 comment#1
BUG=b:448253910
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the output pin widget node IDs for Realtek ALC887 [1] and
use these enums in the motherboard configuration.
[1] Figure 1, Block Diagram, ALC887-GR Datasheet, Rev. 1.0, 24 July 2008
Change-Id: Iaa2ebd7447a19dfc98b006c851f1605851c1ea5d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Because we use dummy ish in pujjoquince, so disable ish related gpio
when fw_config TABLET_MODE=TABLET_MODE_DISABLE
BUG=b:432649211
TEST=Build and boot to OS, check pujjoquince ish related gpio are closed.
Change-Id: Iab43f6d4ce3a6d31358ac0b902535ee3f5dad1e3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In 76e0f64035, it overrides
GPIO_PCH_WP in variant/gpio.h, however gpio.c includes
baseboard/gpio.h instead of variant/gpio.h. The wrong GPIO header
causes the test firmware.WriteProtectCrossystem to fail with the
wrong GPIO_PCH_WP pin number. Corrects the header file included in
gpio.c to fix the issue.
BUG=b:448313028
TEST=Pass firmware.WriteProtectCrossystem
Change-Id: I94b2384d03f8ce83f662a2b9dba4039f3d551b07
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89389
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 1e7908fa9f ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.
Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.
BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker
Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure PWR_EN and RST GPIO of fingerprint sensor.
BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.
Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This moves most of the vendor and architecture independent code into
common ACPI code.
Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Google Fatcat mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use 0 instead of NULL when testing or initializing uintptr_t
fields, since NULL is only defined for pointers.
"data.3.lzma.bin" file is regenerated using:
util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma
dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1
Change-Id: Ia1e7cc5052e842c7ef97ec7cec34919bbe1e2228
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
When commit 50a59d4464 ("device: Add Kconfig to prepare for reworked
verb table implementation") was created this mainboard was not in the
main branch and therefore was not accounted for. However, since it got
merged right before the commit mentioned above was merged, there was no
time to add it.
Add this Kconfig to fix the build system from failing.
Change-Id: If7382125122b4d54332f52d922d8af84ba51763c
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89368
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
*information* does not have plural, so use *This* instead of *These*.
Change-Id: I966373371cac4edd681f3b503e5f3a637fc28913
Fixes: a45c8441af ("lib: Add boot mode information to coreboot tables")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89227
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Seems to be the same board but with a Twin Lake processor.
VBT extracted from vendor firmware. This makes HDMI and
DisplayPort work.
Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89281
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/purism -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: I2ee7a93392a57e8194cc8116c3fc55116336234f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88686
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:
fatal1ty_z87_professional:
- 0x11020011 -> Creative CA0132[3]
It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.
The following chip names were identified using external sources:
b75m-itx:
- 0x10ec0892 -> Realtek ALC892[1][5]
b75pro3-m:
- 0x10ec0892 -> Realtek ALC892[2]
z87_extreme3:
- 0x10ec0892 -> Realtek ALC892[1][6]
z87_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][7]
z87_pro4:
- 0x10ec0892 -> Realtek ALC892[1][8]
z87e-itx:
- 0x10ec0900 -> Realtek ALC1150[4][9]
z87m_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][10]
z87m_oc_formula:
- 0x10ec0900 -> Realtek ALC1150[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asrock -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/ca0132.c:10144
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:844
[5] https://www.asrock.com/mb/Intel/B75M-ITX/index.asp
[6] https://www.asrock.com/mb/intel/Z87%20Extreme3/
[7] https://www.asrock.com/mb/intel/Z87%20Extreme4/
[8] https://www.asrock.com/mb/Intel/Z87%20Pro4/
[9] https://www.asrock.com/mb/Intel/Z87E-ITX/
[10] https://www.asrock.com/mb/Intel/Z87M%20Extreme4/index.asp
[11] https://www.asrock.com/mb/intel/z87m%20oc%20formula/
TEST= All boards passed regression test (CB:88763)
Change-Id: I60ba4e8e048dfbf8ca5969251fd448ce3644d9e0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:
macbookair4_2:
- 0x10134206 -> Cirrus Logic CS4206[1]
It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.
The Kconfigs were reverted using the following command:
find src/mainboard/apple -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] Linux kernel: sound/hda/codecs/cirrus/cs420x.c:770
TEST= All boards passed regression test (CB:88763)
Change-Id: I1fcfa0e5e1af27dc5b0dc77bf471a7636b361cbe
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/amd -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: Ie8dcff7caa24ec9f671159ea39a46989a98a6fbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88659
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:
g43t-am3:
- 0x10ec0888 -> Realtek ALC888[1]
The Kconfigs were reverted using the following command:
find src/mainboard/acer -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] coreboot board status: kernel_log.txt
TEST= All boards passed regression test (CB:88763)
Change-Id: I36cccc7033b3df523ff1c0d1891ef194090fe50e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88658
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/51nb -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: Ib77a7d097b0ae68d250ebe0cb269249a587efcb3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This rework is done gradually, and that means different mainboards will
use different implementations of the verb table. As this code is used by
multiple mainboards we need to keep both implementations and select
whichever implementation matches the one being used by the mainboard
currently being built.
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST=
1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
identical binaries (tested with google/slippy_falcon)
2. Passed regression test (CB:88763)
Change-Id: I3bf8140a4ceb6edad71d57ab82e0a96f51159985
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88739
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This rework is done gradually, and that means different mainboards will
use different implementations of the verb table. As this code is used by
multiple mainboards we need to keep both implementations and select
whichever implementation matches the one being used by the mainboard
currently being built.
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST=
1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
identical binaries (tested with google/auron_paine)
2. Passed regression test (CB:88763)
Change-Id: I9ba3259defae66678c4490891b869b96b6c6ade3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The current implementation of the HDA verb table has been shown to have
some problems. The primary issue is that it requires the programmer to
keep track of the amount of verbs that are going to be loaded. While
this may sound simple, in practice there have been numerous cases where
this "count field" has been forgotten to be updated or miscounted. In
the case where the "count field" is incorrect, coreboot will start
looking for codecs in some random memory location, essentially making
loading further codecs impossible.
Another issue is the "count field" treats 4 32-bit values as a single
group, therefore the amount of verbs in the table must be a multiple
of 4. This makes intuitive sense when only using the AZALIA_PIN_CFG() or
AZALIA_SUBVENDOR() macros. However, once the verb table requires
"controls" that use < 4 verbs (e.g. "Coefficient Index"), we need to add
padding values to ensure the alignment is correct. This adds unnecessary
verbs to the table which can further lead to unnecessary processing.
Therefore, in this change we proprose a solution by separating the codec
entries in the verb table into structures, which allows us to separate
the verbs into an array and automatically calculate the "count field"
using the ARRAY_SIZE() macro. It also makes iteration and access to
member fields easier. We also now count the verbs and not 4 32-bit
groups, eliminating the aforementioned alignment issue.
Additionally, this change also changes the way coreboot searches for
entries in the verb table. Before, we searched the table for only a
matching vendor ID, but now we search for a matching vendor ID and
codec address pair. This allows a mainboard to be able to correctly load
multiple audio codecs that use the same chips.
To make reviewing this large rework easier, we temporarily keep both
implementations (legacy and reworked) and allow boards to choose which
implementation to use by selecting a Kconfig. Newer boards are
discouraged from using the legacy implementation, as it is not selected
by default. This allows us to slowly change the codebase instead of
changing everything at once.
TEST=
1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
identical binaries (with INCLUDE_CONFIG_FILE=n)
2. HP ProBook 450 G3 using reworked verb table was able to load all
verbs successfully.
Change-Id: Ib16237de89956405afa3be5b4e3f64a4d62e6a48
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88656
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new Kconfig which tells the mainboard is using the "legacy" verb
table implementation. This is only needed during the transition towards
the reworked implementation, and will be removed once completed.
The Kconfigs were added manually and not with a script.
Change-Id: I3806cc8df4e244ee6542ad6796ccd9e36de557e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89174
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a new library, `vga_gfx`, to handle text
rendering on a VGA planar buffer. The new functionality supports
displaying text with various screen orientations (Normal, Left Up,
Bottom Up, and Right Up).
The key features are:
- A new public API, `render_text_to_bitmap_buffer()`, that takes a
text string, screen orientation, and buffer as input.
- Automatic text wrapping to fit the screen's effective width,
considering the specified orientation.
- The `vga_gfx.c` library is conditionally compiled for both
`romstage` and `ramstage` based on `CONFIG_VGA` and
`CONFIG_ROMSTAGE_VGA` respectively.
- Text is rendered as a 1-bit-per-pixel bitmap and then cropped
to its bounding box to optimize the output size.
- The `bootsplash.h` header file is updated with the new API
prototype and related constants.
This implementation allows for flexible text display, which is
crucial for showing user notifications on devices that may
operate in a rotated display mode.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I80fcf0a3f106a44f8e4ecdeec38f54ff09f86e6f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch enables fingerprint sensor in devicetree for ojal and updates FW config for GPIO's config according to schematics revision 0.9.
RDC kit no:840138
BUG=b:437459757
TEST=Build ojal board and check dmesg for FPS detection.
Change-Id: I44a24423f4d5b1fc85a5b3bb51f2d6646c82f9dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89324
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables ELAN touchpad in devicetree on I2C0 interface and updates FW config for GPIO's according to schematics revision 0.9.
Intel RDC kit no:840138
BUG=b:437459757
TEST=Build ojal board and test trackpad functionality
Change-Id: Idf84165877e98df31f71c8df916637a455ce84dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch also provides valid 'io_port_mmio_base', which is the addr of
VIRT_FW_CFG device @0x1010_0000 used to convey ACPI & SMBIOS info.
TEST=build and run successfully on QEMU rvvirt machine.
Change-Id: I3cfd3020f1edacbc647188ab232c0a35dbd71f74
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".
Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The 'id' in OTHER_HSL macro is non-typed, downflow would occur when
‘id’ is unsigned and less greater than hart_id. Cast it to int.
Change-Id: I777337b7e374024aff6fb36de603b799b1a65371
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.
This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.
Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled
Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)
Not working:
- S3 sleep
Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to align
with the naming conventions used for other FSP-M configuration
functions.
Change-Id: I0044c21a8f82dfa2308fade78adbd8bcf844cb63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
I found a typo in the comments, so I fixed it.
It seems that 'this operations' is a typographical error.
Change-Id: Ic272e122ce180dee8c0516ecea27cd10932c2363
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PPC64 is not functional without [OPAL] with which Linux kernel
communicates to implement important functionality like a TPM driver.
In addition to providing runtime services via OPAL Skiboot also handles
some parts of the boot process (like extracting kernel from flash) and
adjusts device tree as needed.
coreboot does not currently implement OPAL and is not likely to do it
any time soon (if ever), so must use Skiboot as a second-stage firmware
to have a fully functional PPC64 device.
mb/raptor-cs/talos-2/Kconfig is updated because Skiboot doesn't fit into
512 KiB image.
[OPAL]: https://open-power.github.io/skiboot/doc/opal-spec.html
Change-Id: I49ad6094acaccf731ab6d6b45ac103d485a3179c
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Table is from vendor.
Decrease HWEQ high pass filter from 300Hz to 125Hz.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: Id8f20af4b37cb84ec1720e7c36082c7f8cf9abb1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89284
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.
BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.
Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add support for Class-D Smart Amplifiers: CS35L56, CS35L57 and CS35L63.
CS35L56 and CS35L57 are 18.5 V Class D Smart Amplifiers with Multi-Cell
Battery Boost.
CS35L63 is a PC Smart Amplifier with Speaker Protection and Audio
Enhancement Algorithms.
The driver was written based on the Datasheets for these parts and
generates the audio SSDT information for the amplifiers. Since all
three parts are part of the same family they all have similar SoundWire
settings.
The user can configure which part, SSID and Speaker ID is generated in
ACPI, as well as define each amplifier's Soundwire Unique ID and Link
ID.
These parts support DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.
These parts also support the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.
This is currently only tested using QEMU using example configuration:
chip drivers/soundwire/cs35l56
# SoundWire Link 2 ID 3
register "desc" = ""Left Speaker Amp""
register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
register "sub" = ""12345678""
device generic 2.3 on end
end
Which produces the ACPI:
Device (SW23)
{
Name (_ADR, 0x00023301FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0F)
{
Package (0x02)
{
"mipi-sdw-sw-interface-revision",
0x00010000
},
[...]
Package (0x02)
{
"mipi-sdw-source-port-list",
0x18
},
Package (0x02)
{
"mipi-sdw-sink-port-list",
0x06
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x06)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
},
Package (0x02)
{
"mipi-sdw-dp-0-subproperties",
"DP0"
},
Package (0x02)
{
"mipi-sdw-dp-1-sink-subproperties",
"SNK1"
},
Package (0x02)
{
"mipi-sdw-dp-2-sink-subproperties",
"SNK2"
},
Package (0x02)
{
"mipi-sdw-dp-3-source-subproperties",
"SRC3"
},
Package (0x02)
{
"mipi-sdw-dp-4-source-subproperties",
"SRC4"
}
}
})
Name (BRA0, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x04)
{
Package (0x02)
{
"mipi-sdw-bra-mode-min-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-data-per-frame",
0x01D6
},
Package (0x02)
{
"mipi-sdw-bra-mode-min-us-between-transactions",
Zero
}
}
})
Name (DP0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x07)
{
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x01)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
}
}
})
Name (SNK1, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0C)
{
Package (0x02)
{
"mipi-sdw-data-port-type",
Zero
},
Package (0x02)
{
"mipi-sdw-max-grouping-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-imp-def-dpn-interrupts-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-modes-supported",
One
},
Package (0x02)
{
"mipi-sdw-max-async-buffer",
Zero
},
Package (0x02)
{
"mipi-sdw-block-packing-mode",
One
},
Package (0x02)
{
"mipi-sdw-port-encoding-type",
One
},
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
Package (0x02)
{
"mipi-sdw-simplified-channelprepare-sm",
Zero
},
Package (0x02)
{
"mipi-sdw-port-channelprepare-timeout",
Zero
},
Package (0x02)
{
"mipi-sdw-channel-number-list",
Package (0x02)
{
Zero,
One
}
},
Package (0x02)
{
"mipi-sdw-channel-combination-list",
Package (0x01)
{
0x03
}
}
}
})
Name (SNK2, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC3, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC4, Package (0x02)
{
[... same as SNK1 ...]
})
}
Change-Id: Ie04020f008862051f26e0101828b5944d212e706
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boardview shows the COM port header is connected to serial port A on the
super I/O chip while serial port B pins are unconnected, but it has been
coded for serial port B which cannot be correct.
Change to initialize serial port A instead.
This aligns it with other variants in the family, allowing it
to take advantage of future bootblock code unification.
Change-Id: I8c1a46bef7d9c89f423f8fea9a826b9549d783b4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found on many Asus P8x7x series mainboards, NCT5535D is a 64-pin LPC
super I/O chip with no publicly available datasheet. However, it appears
to share the same silicon as NCT6779D. With only half the pins of 6779,
it does not have parallel port, serial port B, or GPIOs 1 and 6.
This patch adds header and Kconfig option for 5535, and adapts 6779
code to also supply C code to 5535 as well.
asus/p8z77-v_lx2 still builds once modified for this chip, but is not
tested further.
Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds long overdue power loss resume support to nct6779d using
code from nct5572d.
Change-Id: I91bf01a176716b97c6ca6a841c68cd3d4a39d23d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88701
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
