mb/google/trulo/var/pujjocento: Update DTT settings for thermal control

The DPTF parameters were defined by the thermal team.
Based on thermal table in b:448253910 comment#1

BUG=b:448253910
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/pujjocento/overridetree.cb

@@ -215,8 +215,10 @@ chip soc/intel/alderlake
 				register "controls.charger_perf" = "{
 					[0] = { 255, 4700 },
 					[1] = {  40, 2500 },
-					[2] = {  16, 1000 },
-					[3] = {   8,  500 }
+					[2] = {  32, 2000 },
+					[3] = {  24, 1500 },
+					[4] = {  16, 1000 },
+					[5] = {   8,  500 }
 				}"
 
 				device generic 0 on