Enable clocks for Type-C ports C0 and C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
BUG=b:448107633
TEST = Verified that all the clocks added are ON during usb init.
BIT31[CLK OFF] of CBCR register of respective clock indicates
clock status.
Clock Configuration Status:
Clock Name State Register Value
----------------------------------------------------------------
gcc_usb30_mp_master_clk ON 0x00117018 0x00000001
gcc_usb30_mp_sleep_clk ON 0x00117024 0x00000001
gcc_usb30_mp_mock_utmi_clk ON 0x00117028 0x00000001
gcc_usb3_mp_phy_aux_clk ON 0x00117288 0x00000001
gcc_usb3_mp_phy_com_aux_clk ON 0x0011728C 0x00000001
gcc_usb3_mp_phy_pipe_0_clk ON 0x00117290 0x00000001
gcc_usb3_mp_phy_pipe_1_clk ON 0x00117298 0x00000001
gcc_cfg_noc_usb3_mp_axi_clk ON 0x001173CC 0x00000001
gcc_aggre_usb3_mp_axi_clk ON 0x001173D0 0x00000001
gcc_sys_noc_usb_axi_clk ON 0x0012D014 0x00000001
gcc_cfg_noc_usb_anoc_north_ahb_clk ON 0x0012D028 0x00000000
gcc_cfg_noc_usb_anoc_south_ahb_clk ON 0x0012D02C 0x00000000
gcc_aggre_usb_noc_axi_clk ON 0x0012D034 0x00000001
gcc_cfg_noc_usb_anoc_ahb_clk ON 0x0012D024 0x00000000
gcc_usb30_prim_master_clk ON 0x00139018 0x00000001
gcc_usb30_prim_sleep_clk ON 0x00139024 0x00000001
gcc_usb30_prim_mock_utmi_clk ON 0x00139028 0x00000001
gcc_usb3_prim_phy_com_aux_clk ON 0x00139064 0x00000001
gcc_usb3_prim_phy_pipe_clk ON 0x00139068 0x00000001
gcc_cfg_noc_usb3_prim_axi_clk ON 0x0013908C 0x00000001
gcc_aggre_usb3_prim_axi_clk ON 0x00139090 0x00000001
gcc_cfg_noc_usb3_sec_axi_clk ON 0x001A108C 0x00000001
gcc_aggre_usb3_sec_axi_clk ON 0x001A1090 0x00000001
gcc_usb30_sec_master_clk ON 0x001A1018 0x00000001
gcc_usb30_sec_sleep_clk ON 0x001A1024 0x00000001
gcc_usb30_sec_mock_utmi_clk ON 0x001A1028 0x00000001
gcc_usb3_sec_phy_aux_clk ON 0x001A1060 0x00000001
gcc_usb3_sec_phy_com_aux_clk ON 0x001A1064 0x00000001
gcc_usb3_sec_phy_pipe_clk ON 0x001A1068 0x00000001
Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This doesn't do anything, so remove it.
Change-Id: Ic753d0f08bdc0e9dd839357eb73c9771d94e5c83
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There are three options for the LID switch:
SWITCH_NORMAL 0x00
SWITCH_SLEEP_ONLY 0x01
SWITCH_DISABLED 0x02
Add these to coreboot to ensure they are set correctly.
Change-Id: I159111438eabd4abeb654be75fd80f29bd835055
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure Pin Mix for Cs, Clk, Miso and Mosi to get the eSPI
GPIOs working as they should be.
Change-Id: I798f1e98f611a53e9c87f15e1e0f1679b9933bee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89520
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common settings are:
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFPx that are not present.
* eDP panel colour depth is 24-bit (8 bpc).
* POST brightness of 100.
* Minimum brightness of 0.
* DPST level of 2.
* PSR Enabled.
* DDRS Enabled.
Test=Boot all boards, check brightness levels are consistant, the
kernel recognises that PSR and DDRS are enabled, check all outputs
work.
Change-Id: I7eb6a110d25d4bcfd26ffdddd9ec666fc90a04b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89515
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macro USB2_PORTS_MID vs USB2_PORTS_TYPE_C essentially enables
or disables the PortResetMessage. This is only relevant to TCSS
ports.
Correct the macros accordingly.
Change-Id: I18a078c7f6fb937293e6159f05587b7e1f881512
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89513
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't supported so remove it.
Change-Id: I8e8a87f1394199d3288ae27601069ad88e2fa74f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...
According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.
BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.
Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also adds a missing trailing '/' to util/gitconfig, as this is a
directory.
Change-Id: Ib45dbf161b773cd89ad5acee183aeceac4d29584
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89506
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was moved to commonlib in commit dc9f5cd546 ("coreboot: introduce
commonlib"), then subsequently moved into commonlib/bsd in
commit ea619425ee ("commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/").
Change-Id: Ib92c89cd090e78c76931000925ea6292e1783e28
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was renamed to util/qualcomm in commit 101098c41a
("sdm845: Combine BB with QC-Sec for ROM boot").
Change-Id: I14c9b6d918d30e1d156559d110ad47e556645d84
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add the Elan touchpad configuration for moonstone AVL.
BUG=b:442964901
TEST=build firwmare and check the touchpad can work well in ALOS.
cat /sys/bus/i2c/devices/i2c-12/i2c-ELAN0000\:00/name
i2cdetect -y -r 12 -> 0x15 = UU
Change-Id: Ie105906fb54383dbf91513f81ab933653162ad4e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89467
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:442964901
TEST=emerge-fatcat coreboot and focaltech touchscreen can work well.
Change-Id: I7fb2f8b3c4ceb9d4bc7471d7eef23b0a18dca78a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89465
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable _CRS method when EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is
configured, even without EC sync IRQ support.
Previously, the _CRS method was only generated if EC_ENABLE_SYNC_IRQ or
EC_ENABLE_SYNC_IRQ_GPIO was defined, causing LPC generic memory range
configuration to be skipped on boards that don't use EC sync IRQ which
will results in no communication between kernel and EC.
This change ensures LPC memory range resources are properly exposed
in ACPI considering the hardware limitations where the EC sync IRQ GPIO
is not available for boards using LPC_GENERIC_MEMORY_RANGE.
BUG=437459757
TEST=Build and verify EC LPC memory range is configured in ACPI tables
on boards with EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled
by dumping ssdt tables and also verify 'ectool version' cmd.
ectool version
RO version: ojal-0.0.0-2db24f9+
RW version: ojal-0.0.0-2db24f9+
Change-Id: If63dd631029d2756451fad71a5556bc0b23f507d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89420
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The document is no longer accessible at the original URL.
Change-Id: I9601b3fb9a86796dafd742961d3d130fb735804e
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89463
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard family is set based on the baseboard.
TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.
Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.
TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.
Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for taking the ifdtool platform parameter via the cmd
line, as well as the output directory. Add double quotes around
variables as needed. Add help output describing new parameter options.
TEST=run script against images from skl, adl, and mtl platforms.
Verify no warning from ifdtool that platform is unknown.
Change-Id: I4a27c9876bf639579b791c894b2cbfdae7ab63c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Introduce a Kconfig option EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC for
reading firmware configuration from Unified Firmware and Second-source
Config (UFSC) [1] from EC CBI. As the UFSC already includes both the
32-bit FW_CONFIG and 32-bit SSFC, this option is incompatible with
EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG.
Also check the size of the data read from CBI.
[1] https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6974727
BUG=b:448300592
TEST=emerge=skywalker coreboot
BRANCH=none
Change-Id: I2f686838d2f7a6f3eec3bd5224f89389340f7471
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The changes focus on offering power state current thresholds and Thermal
Design Current (TDC) mode settings.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I25b6b9d2bf19ade51e39db06298ffaef98a7897e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88043
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the MMU configuration for the DMA region by moving
the logic from mmu_cmops.c to the common/mmu_operations.c. This
centralization simplifies the code and removes duplication.
The following changes are included:
- Deleted src/soc/mediatek/common/mmu_cmops.c
- Moved DMA region configuration to mtk_mmu_after_dram
- Updated Makefiles to remove references to the deleted file
BRANCH=none
BUG=none
TEST=emerge-kukui coreboot -j && emerge-elm coreboot -j && \
emerge-rauru coreboot -j
Change-Id: I06289afa74248d55fc1eabeef2f6591bc805a8cf
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89411
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macros being removed are already defined in the soc/memlayout.h.
Remove the duplicated definitions and include the common header instead.
BUG=none
TEST=emerge-asurada coreboot
Change-Id: I38d9ca2310fbc60bb453b9731203ffb0251cb444
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89410
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.
BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot
Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The E6400 and E7240 were updated to use a variant scheme in commit
f62734976c ("mb/dell: Convert E6400 into a variant") and commit
511872dae3 ("mb/dell: Convert Latitude E7240 into a variant"),
respectively, which changed the names of the directories they were
located in. Update MAINTAINERS to reflect this.
Change-Id: If35e5a0afe214fe623334e90969cc7f95d579a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Options are organized to be as close to vendor firmware as possible.
Some options are not implemented for all variants. Those are either
excluded from build via preprocessor, or left visible but unused.
They will be squared off later.
TEST=abuild tested on the whole series.
TEST=Complete platform setup menu appears for mb/asus/p8z77-v_le_plus
with edk2/mrchromebox payload, with changes to front audio panel type
reflected in hardware.
Change-Id: I558012b28d098a90863e3ff6610017c2410c23ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Because the name NINJA has 2 occurrences inside remote recovery.conf:
https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf
Running 'crosfirmware.sh ninja' will list both NINJA and VORTININJA
"file= & url=" with a total of 4 lines instead of 2. Since the script
by default uses the last 2 lines it will prefer VORTININJA and download
the Octopus MEEP recovery image instead while NINJA was requested.
By adjusting 'grep' its matching control by adding '-w' restores the
correct behaviour of only showing 2 lines for the requested image.
Both NINJA, VORTININJA and a third recovery image TIDUS still download
and extract correctly when applying this fix.
TEST=crosfirmware.sh ninja #downloads and extract correct image
Change-Id: I9b55c5a2626339e70f0ada9b80c9488a5580d371
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.
Changes include:
- Declaring new memory regions in symbols_common.h.
- Defining base addresses and sizes for these regions in memlayout.ld.
- Marking these regions as reserved in soc_read_resources() to
prevent overwrites by coreboot.
- Modifying CBMEM top address.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Devices utilizing the second SKU of the SoC experience system hangs due
to missing DVFS support. This patch adds DVFS support for the second
SKU to resolve this issue.
BRANCH=rauru
BUG=b:443664123
TEST=verify booting on both original and second SoC SKUs
Change-Id: If17ecd4a8358e08a45c4662bb92138b7a939512e
Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was supposed to be checked in the regression test script
(CB:88763), however it turns out Valgrind's Memcheck only works on the
heap memory and is unable to catch such errors.
The regression test script was modified to use AddressSanitizer which
can catch such errors, so this should not be a problem in subsequent
changes during the verb table rework.
To be safe, the previously merged commits were also checked with the new
regression test script:
f634121fa4 ("mb/purism: Replace verb tables with reworked implementation")
20d4042458 ("mb/asrock: Replace verb tables with reworked implementation")
2b7dbf80c9 ("mb/apple: Replace verb tables with reworked implementation")
970249694f ("mb/amd: Replace verb tables with reworked implementation")
94beaa7ab3 ("mb/acer: Replace verb tables with reworked implementation")
f3db3a19d5 ("mb/51nb: Replace verb tables with reworked implementation")
However, the following mini-HD code was checked manually, as figuring
out how to strip out minihd_init() was not worth the effort:
bc92d9a666 ("nb/intel/haswell/minihd.c: Add reworked verb table implementation")
69781b9806 ("soc/intel/broadwell/minihd.c: Add reworked verb table implementation")
Change-Id: Iea964fb8b92814b57d4c82412c47cf31fa48de66
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:
h61m-a_usb3:
- 0x10ec0887 -> Realtek ALC887[1][5]
h61m-cs:
- 0x10ec0887 -> Realtek ALC887[1][6]
p8h61-m_pro:
- 0x10ec0887 -> Realtek ALC887-VD[3]
p8h67-i_deluxe:
- 0x10ec0892 -> Realtek ALC892[3][7]
p5gc-mx:
- 0x10ec0892 -> Realtek ALC662[2]
p5qc:
- 0x10ec0888 -> Realtek ALC1200[2]
p5ql-em:
- 0x10ec0888 -> Realtek ALC1200[8]
p8z77-m:
- 0x10ec0887 -> Realtek ALC887[1][9]
p8z77-v:
- 0x10ec0892 -> Realtek ALC892[3][10]
p8z77-v_le_plus:
- 0x10ec0889 -> Realtek ALC889[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asus -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see commit 31fc5b06a6
("device: Introduce reworked azalia verb table").
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc882.c:839
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:842
[5] H61M-A/USB3 User's Manual (English), Version E8184
[6] H61M-CS User's Manual (English), Version E9069
[7] P8H67-I Deluxe User's Manual (English), Version E6964
[8] P5QL-EM user’s manual(English), Version E4165
[9] P8Z77-M User's Manual (English), Version E7075
[10] P8Z77-V User's Manual (English), Version E7074
[11] P8Z77-V LE PLUS User's Manual (English), Version E8001
TEST= All boards passed regression test (CB:88763)
Change-Id: Id2d4895bb40885f83d602b3a80805a84e348771b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This board uses PCI to send POST codes to the NC FPGA. Enable the
feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visible in coreboot.
TEST=Built and booted on mc_rpl1. Check that the POST Codes are
correctly displayed on the 7-segment display.
Change-Id: I95a1ac7121560b812aea36485c37f39e13de535a
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All mc_rpl boards have, like the mc_apl and mc_ehl variants, legacy
PCI devices which take longer to boot. To ensure their correct
enumeration, a delay is added before the PCI scan starts. The delay
value is provided by hwinfo.
TEST=Built and booted on mc_rpl board. Verified legacy PCI devices
enumerate correctly after delay implementation. Log excerpt while
testing function:
```
[INFO ] tlcl2_extend: response is 0x0
[DEBUG] TPM: Digest of `CBFS: hwinfo.hex` to PCR 3 measured
[NOTE ] Wait remaining 6595702 of 10000000 us for legacy devices...done!
[DEBUG] BS: BS_DEV_ENUMERATE entry times (exec / console): 6597 / 64 ms
[INFO ] Enumerating buses...
```
Change-Id: I97885a7cf060bc69c7fef75a9fa917bc8a176582
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89393
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
