Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Id7b68e7c5ed554639dc14e837e311552c3ff92f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: I3a4b122b206cb1fc98e693973f2aeb28e8b2ff22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86814
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces power consumption so enable it. For example,
`starbook/adl_n` idles at 5.16W with this disabled, but 4.6W with
it enabled.
Change-Id: I5b6fd4853aba0dd4e9f9f45be4b43efff375dfad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up Energy Efficient Turbo to devicetree so it can be configured.
The default value of 0 will ensure this doesn't change existing boards.
Change-Id: I58a9877371ec66e71cee15aced2413a282416b5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86855
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be set to the opposite of lockdown_by_fsp.
Change-Id: I9e3c8f03ca14d2cb28c3f2f9bd74618d81e53d2c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86854
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCO SMI handler clears the watchdog timeout flag unconditionally.
Since the system is only rebooted if the flag is already set and the
watchdog timer expires again, this means that the reboot never occurs.
This change preserves the timeout flag if CONFIG_ACPI_WDAT_WDT is
enabled, otherwise the behavior remains unchanged.
TEST=Build CB with CONFIG_ACPI_WDAT_WDT=y and
CONFIG_USE_PM_ACPI_TIMER=y, trigger the watchdog under Linux
with "wdctl -s 5 && cat > /dev/watchdog" and wait approximately 10
seconds (two watchdog periods) for the watchdog to reboot the system.
Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84875
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
FW Init Complete is a prerequisite for sending the FW FEATURE SHIPMENT
TIME STATE OVERRIDE message. Unfortunately, on some platforms such as
Lenovo ThinkCentre M700 Tiny, it takes too long for the flag to be set,
so enabling PTT fails.
Wait up to 5 seconds for the FW Init Complete to be set instead of
failing immediately.
On M700 Tiny with debug level set to ERROR, we have to wait nearly 2
seconds:
[EMERG] HECI: CSE took 1900 ms to complete FW init
Because FW Init Complete is not required for getting the current feature
enablement state, only for setting, move the FW Init Complete check to
after we've determined if we actually need to change the state. This
avoids needlessly increasing boot time.
Reference: Intel ME 11.x BIOS Specification, #549522, section 6.3.15
Change-Id: Ib6de170f3f998273bec437848faa49652f013f45
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84862
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been observed that at least on some M700 Tiny boards, CLKREQ
signals aren't wired as per the schematic. Disable them and configure
their pads as per original Lenovo UEFI.
This change fixes Wi-Fi card detection on M700 Tiny.
TEST=Boot M700 Tiny with AX200 card in Wi-Fi card slot and boot to
Windows 10. Check that Wi-Fi works correctly.
Change-Id: I5b26937cd4a6937b516304fefad9186b9e1cdc76
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84813
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coolstar's Windows drivers require the IOM device to be visible to the
OS, so add a Kconfig to control this, which mainboards will select in
subsequent patches.
TEST=build/boot Win11 on rex/screebo, verify USB4 drivers functional.
Change-Id: I00ef9703179d87b7b476ef18d8d02fcafa9e14ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86792
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 'ctags' target.
we can see that 'make help' says
...
ctags / ctags-project ...
...
but, Makefile have only 'ctags-project' target.
Change-Id: Ie554892bcb072d773babf745d7756630327d2975
Signed-off-by: melongmelong <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85936
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ] EnableTcssCovTypeA[0]= 0x00000000
[SPEW ] MappingPchXhciUsbA[0]= 0x00000000
[SPEW ] EnableTcssCovTypeA[1]= 0x00000001
[SPEW ] MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf
BUG=b:400809281
TEST=Able to build and boot google/Riven
Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly-created ACPI devices in common/acpi, to align with other
client SoCs.
Change-Id: Icc5da0b820101b3c651ed59a47aeab37440a6996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Iabd9dec2f6838c1dc4b1cad924ceb62c992f89c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
HEC1 and SRAM are defined in src/soc/intel/meteorlake/chipset.cb:
device pci 16.0 alias heci1 on end
device pci 14.2 alias pmc_shared_sram off end
Add entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors
in the kernel dmesg log, and add entries to soc_acpi_name() to ensure
that these names are returned during acpi_device_path() calls.
TEST=Build/boot Linux 6.x on screebo to confirm errors are not seen.
Change-Id: Id79054d2cb56daae238ac562b7b6c204926cdced
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86797
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The ACPI device path name handler for the fast SPI device is missing,
so add it to ensure that the names is returned from acpi_device_path()
calls.
TEST=Build/boot Win11 on screebo
Change-Id: Ibf5ab3bf6694875c357b999fe871a5b16f89ec62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These can be used by most/all client SoCs
Change-Id: I6622fa34f014bbe9fdd95a996332dfe5a07a92fb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.
Correct this by setting the scope of the IOM device to just _SB.
TEST=build/boot Win11 on google/drobit, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.
Change-Id: Ia089e723ccac5508cfaffc0204815b80bb209dd0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86819
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.
Correct this by setting the scope of the IOM device to just _SB.
TEST=build/boot Win11 on google/banshee, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.
Change-Id: I7e61341dd9b7548a079a1ce3b88025f6391f3203
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit introduces a driver for the Intel Touch Controller (THC),
which supports HID-over-I2C and HID-over-SPI protocols, as well as
touch devices. The driver generates ACPI objects and publishes data
into the Secondary System Descriptor Table (SSDT) to facilitate
interaction with the touch hardware.
The driver implementation covers the following ACPI objects:
- _DSM (Device Specific Method)
- _CRS (Current Resource Settings)
- _STA (Power resource with Status), including _ON and _OFF methods
- _DSD (Device Specific Data) for THC-I2C
- _RST (Device Reset) for THC-SPI
Template device configuration for the following supported devices:
- Wacom: SPI touchscreen only
- Elan: both SPI and I2C touchscreen
- Hynitron: I2C touchpad only
It also includes template configurations for supported devices such as
Wacom (SPI touchscreen), Elan (SPI and I2C touchscreen), and Hynitron
(I2C touchpad). These configurations are divided into device-specific,
SoC-specific, and motherboard (MB)-specific details.
For SoC-specific configuration, the driver implements functions like
`soc_get_thc_hidi2c_info` and `soc_get_thc_hidspi_info`, which should
be defined in the SoC's `chip.c` file. Device-specific configurations
are provided by the driver for supported devices. For unsupported or
generic devices, the required information is expected to be provided
via the device tree. MB-specific information, such as LTR (Latency
Tolerance Reporting) values and speed, must be provided in the device
tree.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has
the necessary touch configurations. Verify that the THC ACPI tables are
correctly generated in the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit a7a76b0dee ("soc/intel/meteorlake: Hook up FSP repo for IOT")
added logic to use the FSP repo for IOT boards, but in doing so
broke the automatic selection of FSP_USE_REPO when HAVE_INTEL_FSP_REPO
was selected. Fix this by removing the override for FSP_USE_REPO and
selecting HAVE_INTEL_FSP_REPO when FSP_TYPE_IOT is selected.
TEST=build/boot starlabs/starbook_mtl with IOT FSP binaries/headers
Change-Id: Iad946a23c569e27cafa35ce2e6fefd6be1d90666
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86845
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This reverts commit 491afc3cc7.
Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and
'PchPciePowerGating' UPDs are also available on ADL-N.
Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Modify the config for GPP_F09 to poweroff successfully.
BUG=b:388202483
TEST=Build felino and poweroff under the OS and the dut can poweroff successfully.
Change-Id: I1c83d230be7dbce9f9ad0b55f86d748e2de3565e
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86808
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Go through the schematics and update GPIOs for the unit. In particular,
explicitly mark unconnected pins and pins without placed components as
not connected.
Change-Id: I5a81115850d7bf3ecabeae29058e86cea51ac390
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84149
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit rectifies a PIN mapping error in GPIO Community 3,
introduced by the removal of CPUJTAG PADs from the static ACPI entry.
CPUJTAG PADs are reserved for SoC debugging and should not be
configured by kernel drivers. To ensure accurate PIN mapping for
subsequent GPIO banks, this patch designates the CPUJTAG PAD range as
"RSVD" (Reserved) and exposes the corresponding GPIO PIN numbers. This
allows other GPIO banks within Community 3 to correctly adjust their
offsets.
Problem:
Prior to this fix, GPP_H0 was incorrectly assigned PIN 0 within GPIO
Community 3, deviating from the EDS.
Solution:
By marking the CPUJTAG range as RSVD, GPP_H0 is now correctly mapped
to PIN 15, aligning with the EDS definition.
Changes in details:
- Corrected the GPI3 to accurately calculate the GPIO PINs.
- Renamed CPUJTAG to RSVD (Reserved) and adjusted related definitions.
- Updated GPI3 device to reflect the RSVD group, including adding
subproperties and correcting group counts.
- Modified gpio_defs.h and gpio_soc_defs.h to reflect the RSVD name
change and pad count.
Change-Id: I9f32b54a8a0218cd993f01ccf5f0bb158877766a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86825
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies the get_lid_switch() function to allow faking the
lid switch state when the GBB_FLAG_DISABLE_LID_SHUTDOWN Kconfig option
is enabled.
When GBB_FLAG_DISABLE_LID_SHUTDOWN is enabled, the function will
always return 1 (lid open), bypassing the actual lid switch state
retrieval from the Embedded Controller (EC).
This functionality is specifically designed to facilitate factory
processes, such as netboot image downloads, where devices need to
remain operational regardless of the lid's closed state. This prevents
intended shutdowns triggered by a closed lid during manufacturing and
testing.
By setting GBB_FLAG_DISABLE_LID_SHUTDOWN, we override the actual
lid status with a simulated LID status is open, which is a
prerequisite for display initialization.
w/o this patch:
```
[ALERT] Graphics hand-off block not found
...
[INFO ] NAME | PORT | POLARITY | VALUE
[INFO ] lid | undefined | high | low
```
w/ this patch:
```
[INFO ] NAME | PORT | POLARITY | VALUE
[INFO ] lid | undefined | high | high
...
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
[INFO ] x_res x y_res: 1920 x 1200, size: 9216000 at 0xd0000000
```
BUG=b:333982806
TEST=Verified lid switch behavior with and without
`GBB_FLAG_DISABLE_LID_SHUTDOWN` enabled.
Change-Id: I89d506ab50b421b93be13b0e5e36a7ef1247e2b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86807
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the magic number 0x00000001 with the BIT(0) macro for
QCLIB_GA_ENABLE_UART_LOGGING. This improves readability and
maintainability by clearly indicating that a specific bit is being set.
TEST=Able to build google/herobrine.
Change-Id: Ie425a68c6721343ca53eb883d6278decca92bcad
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set PL4 to the wattage of the included AC adapter. The EC will override
this limit at runtime, if necessary (for example, if a weaker USB-PD
power supply is connected).
PsysPmax is set according to the board schematics (RPsys resistor),
which ensures that the Psys signal generated by the battery charger and
interpreted by SOC VRs is interpreted correctly and that Psys power
limits applied by the EC work as expected.
Change-Id: I56e9c20556553940c308150f7e470628f56c3991
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The DDI lane number in `enum ddi_ports` is 1-based, while the TCPx
display link numbers from the SoC are 0 based. Fix the off-by-one error
and set the HDMI DDI lane index to the correct value of 3.
Change-Id: I861e58150ebe8b97cf3e9be81c2bd5494eff600b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86751
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, to make sure that the UEFI setup menu stays legible on HiDPI
displays, the VBT has the Fixed Display feature enabled with the
resolution set to 1920x1200.
If the secondary display feature is also enabled, and a monitor with
resolution lower than 1920x1200 is connected, the result is that neither
the internal nor external display is initialized.
Disable the secondary display feature to ensure that the internal
display keeps working regardless of any connected external displays.
Change-Id: I47630f5ce9573ed0ae86621252a04d41a92d40cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86713
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Split V5x0TU into a separate variant of the mtl-h baseboard. This is in
preparation to add support for the V5x0TNx variants, which is a
different variant of the board, with a discrete NVIDIA GPU.
Change-Id: I4f8215ace6b7a394f8d196be3f81c33b2cb4e9ec
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86709
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set TCSS SOC Aux orientation override as per the mainboard schematic.
Change-Id: I45903f26a3f724e6bd82645b0fe3d1e919a84833
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86697
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all USB configuration from the parent SOC node to the appropriate
XHCI controller device nodes in the devicetree.
Change-Id: Ib702b132698bcb71b4e7b6fa51c6a428bfe77252
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Probing the clock request signal is not required on this board and with
the SSD models the board is sold with.
Change-Id: I51b0d0f2b390912cf8fff45d736e317de31863ed
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Riven cannot boot into OS from 2nd source eMMC, show message
"Something went wrong booting from internal disk" and stop in depthcharge.
According to Intel provides eMMC DLL delay patch that tuning on each
riven different eMMC system to modify eMMC DLL tuning value to improve initialization reliability.
BUG=b:401663746
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Ib36650f2a8fca486c8c89fb9f2ef42452b7a4cfa
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86778
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.
Change-Id: I95ab68d1b5bb73738b5b6f9461d2b7771e75f17a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The MTL FSP headers in github do not include FirmwareVersionInfo.h, so
DISPLAY_FSP_VERSION_INFO_2 needs to be deselected when using FSP
binaries from the repo.
TEST=tested with subsequent patch
Change-Id: I53dae842f545b3d4fe34ded57916f33716777a7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate SPD id for Nanya memory NT6AP512T32BL-J1
BUG=b:401424949
TEST=go run ./util/spd_tools/src/part_id_gen/part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/drawcia/memory/ \
src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt
Change-Id: Icb1a6894307bd27c7d5ea25adb6cf0c8514c661c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86764
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of guessing the default branch by iterating over a list of
branch names, use the branch that is configured as default by upstream.
Change-Id: I628b5a4e5228870c54719577e32dae169b0ceb2e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Refine dptx_get_edid function to read extension edid to bring up 2.8k
120hz OLED panel.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
EQ training pass
Change-Id: If35782950ae02d892ea697580fa4991595c21533
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DisplayID 2.0 extension. Right now, the implementation
only supports 'Type VII – Detailed timing' data block decoding.
Reference: 'DisplayID v2.1a.pdf'
BUG=b:392040003
BRANCH=rauru
TEST=Check FW screen on a panel than supports Display ID 2.0
Change-Id: I1b8a5ab3ada5c8eacc7b6dde3d33ec72b3790960
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to E-EDID A.2_revised_2020.pdf, block maps are optional in
EDID 1.4. If block maps are used then 254 is the maximum number.
Otherwise, 255 is the maximum number. For now, we simply print the
number of extension blocks.
BUG=b:392040003
BRANCH=rauru
TEST=Verify with the panel containing two EDID extension blocks
Change-Id: I2458e3493e74f91af6422b36285bb95e438a29f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Allow a board to use the default turbo ratio by not specifying
turbo_ratio_limit and turbo_ratio_limit_cores in the devicetree.cb.
TEST: Intel PTAT tool no longer complains about 0Mhz turbo frequency.
Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
