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mb/novacustom/mtl-h/devicetree.cb: Disable detect flag on PCIe CLKREQs

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Probing the clock request signal is not required on this board and with
the SSD models the board is sold with.

Change-Id: I51b0d0f2b390912cf8fff45d736e317de31863ed
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Michał Kopeć 2025-03-03 16:11:00 +01:00 • committed by Matt DeVillier
commit e63e54e0e9
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/novacustom/mtl-h/devicetree.cb
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@ -78,7 +78,7 @@ chip soc/intel/meteorlake
register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
@ -93,7 +93,7 @@ chip soc/intel/meteorlake
register "pcie_rp[PCH_RP(11)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"