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mb/google/nissa/var/riven: Modify eMMC DLL tuning value

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Riven cannot boot into OS from 2nd source eMMC, show message
"Something went wrong booting from internal disk" and stop in depthcharge.
According to Intel provides eMMC DLL delay patch that tuning on each
riven different eMMC system to modify eMMC DLL tuning value to improve initialization reliability.

BUG=b:401663746
TEST=Cold reboot stress test over 2500 cycles

Change-Id: Ib36650f2a8fca486c8c89fb9f2ef42452b7a4cfa
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86778
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2025-03-10 10:03:11 +08:00 • committed by Matt DeVillier
commit b9759ba550
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/riven/overridetree.cb
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@ -62,7 +62,7 @@ chip soc/intel/alderlake
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C"
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-42.3.12.