With few exceptions, Nuvoton super I/O chips have the same
configuration registers.
This patch provides a single set of initialization routines to set
up power loss resume, initialize keyboard, and handle switching
PS/2 port role for mainboards with only one PS/2 port.
Power loss resume handling and PS/2 port role switching can be
controlled using nvram or CFR options. Mainboards lacking such
options will need to add them separately.
The common routines support all currently in-tree Nuvoton SIO chips
except nct5104d, nct6687d, npcd378, wpcm450. They will be hooked up
in follow-up patches.
There is also SMM code to disable PS/2 keyboard wakeup before going to
S5, otherwise the system will also power up with any key on the
keyboard, which is most likely undesirable. To use this, mainboards
must set Kconfig SUPERIO_NUVOTON_PNP_BASE, add smm.c to Makefile.mk
and call it from mainboard_smi_sleep().
Update the help text of HAVE_SHARED_PS2_PORT Kconfig with the final
option name used.
TEST=Both power loss resume and PS/2 port role control work on
asus/p8z77-m with entire train of supporting patches applied.
Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
INTRUDER# may be asserted continuously on some Star Labs systems.
Disable routing the event to SMI by default to avoid SMI storms when TCO
SMIs are enabled (e.g. via BOOTMEDIA_SMM_BWP).
This allows boards, like starbook_tgl, which assert INTRUDER# constantly
to boot.
TEST=build/boot starbook_tgl with BOOTMEDIA_SMM_BWP selected
Change-Id: I6a2a188a295cc6be3af2043ea902d45c5bb5b95d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some platforms can have INTRUDER# asserted continuously. If it is routed
to SMI, this can cause an SMI storm and prevent boot.
Introduce SOC_INTEL_COMMON_BLOCK_SMM_TCO_INTRUDER_SMI_ENABLE to control
whether INTRUDER# is routed to SMI, while keeping TCO SMIs available for
other uses (e.g. SPI sync SMIs needed by BOOTMEDIA_SMM_BWP).
TEST=build
Change-Id: I33eb8ce3bee64c95a4d5a6f95a096577d55c742d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91335
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When an existing LPC window covers an IO range, but is bigger or starts
earlier the current code doesn't recognize it. It will open another
window overlapping an existing one.
Check if an existing LPC IO window covers the current one and allow it
to be bigger than the entry.
TEST=Thinkpad X280 still boots and error messages are gone.
Should fix the following line seen in the coreboot log of the Lenovo
T480 and compatible:
[ERROR] LPC: Cannot open IO window: 1604 size 1
[ERROR] No more IO windows
[ERROR] LPC: Cannot open IO window: 1606 size 1
[ERROR] No more IO windows
[ERROR] LPC: Cannot open IO window: 1610 size 10
[ERROR] No more IO windows
Change-Id: I586066238b801d2abb1122698fb4092ee0b2f6b9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91171
Reviewed-by: Ladislav Ezr <ladislav@ezr.cz>
Reviewed-by: Johann C Rode <jcrode82@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Galtic has two Elan touchpad options, and since both use the same i2c
address, the runtime i2c detection performed during SSDT generation
can't distinquish between them, leading to both devices being added
to the SSDT. This isn't a problem for Linux, but Windows can't
deal with two touchpads being enabled and using the same resources.
To mitigate this, add a new fw_config field which allows selection
between the two touchpad models, as well as a fallback option for
all devices which are not configured. Users who need to can set the
touchpad type in the SSFC using ectool, and then coreboot will
enable only the selected touchpad at boot.
TEST=build/boot google/dedede (galnat) after setting touchpad type
in SSFC. Verify correct touchpad selected via fw_config, only one
touchpad entry present in SSDT, and touchpad functional under both
Linux and Windows 11.
Change-Id: I36797eb5c8f262782380f95ff3c2e38443cf00c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit ee599486ac.
Having the touchpad type selectable via CFR causes more user confusion
than is solves; switch to using SSFC/fw_config in a subsequent patch.
Change-Id: Ie35d1db19dd2f22ea19289f60dbd86cbf1fa137e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.
BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.
Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.
Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This change adds support for configuring higher CD Clock frequencies
for VGA SOL initialization during the Pre-Memory phase.
This feature allows BIOS to request specific display core clock
frequencies when VGA support is enabled during MRC training.
The VgaInitControl field in IGPU_PEI_PREMEM_CONFIG has been extended
to include BIT6-7 for CD Clock frequency selection:
* 0: No higher CD Clock required
* 1: 442 MHz
* 2: 461 MHz
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: I82fae0d21bb83ed26aad73b830ed15fcd626a9ae
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90795
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653,b:484162286
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: I6998534e3b9c5909839aceb886ab04a04f394289
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91329
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Verify that a battery is actually present before setting the boot
mode to LB_BOOT_MODE_OFFMODE_CHARGING. This prevents the system
from incorrectly entering a charging state when running on AC power
without a battery connected.
TEST=Build and boot on bluey with and without battery present.
Verify boot mode transitions correctly.
Change-Id: I67098bc06b34c25429daf516f3891c50930209fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Allow the mainboard code to disable USB ports based on GPIO straps,
SKU or user configuration. The mainboard code must implement
mb_usb20_port_override() in romstage to disable USB ports. Ports
that are statically disabled in devicetree cannot be enabled
using this method.
Change-Id: I0fd01e12c05d633695a5fb19ff804e9dc588d6ed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Drop USB OC2#, OC3#, OC4#, OC6#
Those are either pulled high or used as GPIO and used by internal
devices only.
- Disable Port 4, 6, 7. They are unused.
- Add comments with devices connected.
TEST=On Lenovo x220 the USB ports P00, P01, P02, P03, P08, P09, P11,
P13 are still working.
Change-Id: I00b0a36a80b812adb9a4ee976dabb528afd36409
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91233
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow the user to disable PCIe ports that are not required.
Change-Id: Id2d7640255c347c768387408f27e9f5448cbef01
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Automatically use the CFR driver when EDK2 payload and SMMSTORE
are enabled. Selects the UEFI variable option backend by default
when SMMSTORE is enabled.
Change-Id: Ib7cb122dc863d3449c670d1917ebdd2a0a6317d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a build time warning in case the DRIVERS_EFI_VARIABLE_STORE is not
selected, but UefiPayload will have a working firmware menu and will
write non-volatile variables into flash.
Without DRIVERS_EFI_VARIABLE_STORE coreboot will be fully functional,
but the settings made in the firmware menu have no effect at all.
Change-Id: Ib8872297d5d3451834f8ccfdaaee32f23727c178
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.
Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.
Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.
TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.
Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Address x1 slot enumeration issues for certain add in cards (AICs)
during boot. This change implements proper power sequencing and adds
support for AICs that use PRSNT2# signaling instead of ClkReq#. The
x1 slot power rail (X1_PCIE_SLOT_PWR_EN via GPP_A8) is pull-high by
design, with GPP_A08 PAD defaulting to GPI configuration. This enables
slot power during early boot phases. PERST# (GPP_D19) is logically
ANDed with PLTRST#, ensuring PLTRST# de-assertion occurs only after x1
slot power stabilization, maintaining proper PCIe timing automatically.
For scenarios requiring power-off at boot, the following sequence
ensures compliance with PCIe link training timing requirements:
Step 1 (romstage): ClkReq PAD off; PERST# asserted; power off
Step 2 (ramstage at BS_PRE_DEVICE exit): Power on; ClkReq PAD on (if
used)
Step 3 (ramstage at BS_DEV_INIT_CHIPS entry): PERST# de-asserted
The CBI fw_config SD field has been redefined to accommodate different
AIC types:
- SD_BAYHUB: For AICs supporting ClkReq# signaling
- SD_GENSYS: For AICs using only PRSNT2# signaling
BUG=None
TEST=Boot Fatcat board with AIC cards configured via CBI fw_config SD
field (SD_BAYHUB or SD_GENSYS). Confirm PCIe device enumeration
appears correctly in boot log. For instance:
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus ae
[DEBUG] PCI: 00:ae:00.0 [1217/9860] enabled
The device should be seen from lspci command, such as:
ae:00.0 Class 0805: Device 1217:9860 (rev 01)
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I94a7ee2ecd8d3fd83006297ef68f97ff49e47595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90000
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move Gen4 SSD power enable (GPP_B10) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.
Changes:
- Enable GPP_B10 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
- Remove duplicate GPP_B10 configuration from gen4_ssd_pads
- Remove GPP_B10 from ramstage gpio_table
BUG=None
TEST=Boot to OS, check PCIe link speed for SSD.
Change-Id: I969a0d5576b9a229f70a4d01737b7f594876b106
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90523
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the discrete TBT controller driver, and configure the necessary
GPIOs for the Alpine Ridge TBT controller to be fully functional.
Add ACPI to ensure the TBT controller properly handles S3 sleep and
resume. Update the documentation w/r/t TBT functionality.
TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
devices populated, lower USB-C port works for USB data and PCIe.
Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88490
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.
Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.
Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76584
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Add a new driver which enables basic TBT support for the Alpine Ridge,
Titan Ridge, and Maple Ridge discrete Thunderbolt controllers.
This driver will initially be used on the Lenovo T480/T480s and
System76 RPL-HX platform boards.
Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75286
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mc_ehl8 variant has an RTC (RV3028-C7) at SMBus address 0x52, which
falls within the SPD EEPROM address range (0x50-0x57). By default, FSP
write-protects this range.
Disable write protection for mc_ehl8 to allow RTC configuration.
TEST=Boot system into OS and use i2ctools to read out registers
0x00-0x06 of the RTC to verify that the driver set the correct date
and time.
Change-Id: I0e6426f57d7e316a74102b1e5352ce9d334eac02
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91200
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RV3028-C7 driver currently uses i2c_dev_read_at() and
i2c_dev_write_at() for block transfers when accessing RTC registers.
These block transfer functions are not universally supported across all
I2C/SMBus controller implementations in coreboot.
Specifically, the Intel i801 SMBus controller does not implement block
read/write operations, causing the RV3028-C7 driver to fail on platforms
using this controller due to missing transfer ops.
Replace block transfers with byte-by-byte operations
i2c_dev_readb_at() and i2c_dev_writeb_at(). These functions are
supported by i801.
TEST=Verified new SMBus functionality on mc_ehl8 (i801 controller).
Verified I2C functionality still works on mc_ehl2.
Used i2ctools from OS to read out registers 0x00-0x06 and confirmed
values match date/time set in coreboot.
Change-Id: I8a40ae14e62e3acf7c3904a8654c1d58fe4eb813
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91199
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the SMN accessor code from SSDT code to DSDT.
This allows compiletime verification of the ACPI code.
Change-Id: I3cddea079f3bfc37eb4e2b2f4496dce6441b289f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the ACP device is always present in DSDT move the
MSG0 method and helper functions into DSDT. This allows to clean
the common ACP code and reduces differences in the runtime code
pathes. The newly introduced DSDT is also verified at compile time.
Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Windows 11 ACP driver depends on the ACPI _DSD method, thus
add the data based on the UEFI implementation.
TEST=Windows 11 ACP driver reports no issues any more.
Change-Id: I3e193ee0dbf736aab9f7d21927a01992e2f84973
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the ACP ACPI device called ACPD from SSDT to DSDT so that a SoC
or a mainboard DSDT can extend the ACP configuration.
Therefore, drop acpi_device_write_pci_dev() in SSDT. Introduce a STAT
variable in ASL, which defaults to 3 (present, enabled, hidden, not ok)
when the device is set to "off" in the devicetree.cb, since the PCI
device is not actual disabled by FSP. When not disabled in devicetree.cb,
STAT will be overriden in SSDT with the actual device status. The STAT
variable is returned by _STA method.
The ACP child devices where seen on Phoenix and KrackenPoint and not
seen on Rembrandt, Cezanne or Mendocino.
Assume older platforms do not have ACP child devices in ACPI.
TEST=Booted on AMD birman_plus (glinda) and verified ACP is working.
TEST=Set ACP device to off and verified it's marked hidden on Windows 11
Device Manager.
Change-Id: I31c3f01f83f27d0121f9e003e60a7f12d49427f6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Eliminates errors in cbmem log:
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
not found
Change-Id: I562e63365599a2dc62526f5789b7c6c79318cb9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This board does not have a DMIC, so update the verb table to
reflect that.
Change-Id: Idd38dc016d7d178002f291ac8a0088e5f7b7490d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code is copied here for Pantherlake.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: Iacd43774c227fae5edc309dc1e163cc5c87160e4
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91202
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to PantherLake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Panther
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: I10226a2e04905040523d95ba8f5bc56f45606fe6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91201
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This fixes an integer overflow in the calculation of the offset within
the SPD binary that has caused memory detection failures on some
machines (e.g. this resolves https://ticket.coreboot.org/issues/627 ).
In a nutshell, spd_index (uint8_t) receives an assigned multiplication
by 512 (SPD_SIZE_MAX_DDR4) which will always truncate the result.
Change-Id: I048a73c18c9a3d1b20e2a4276e1714e59550eaf5
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91170
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Root complex always resides at 0:0.0 and is always enabled.
Add a static device in DSDT that can be extended later on.
Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Lapis project uses a USB camera and does not have
a MIPI camera, therefore the IPU interface is disabled.
BUG=b:475355637
TEST=emerge-fatcat coreboot
Change-Id: I35273251d73a3f885b7dd8750b746dbca06e9564
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMBus controller was previously disabled on the Lapis variant.
Enable the SMBus device in the overridetree to allow the system to
communicate with onboard peripherals like the SPD EEPROMs and
thermal sensors.
BUG=none
TEST=Build and boot on Lapis; verify smbus is initialized.
Change-Id: I9d7254b6c2686ec67392294d45b870e3670f2aca
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91196
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select HAVE_CHARGING_DEBUG_ACCESS_PORT for the Quartz variant.
BUG=b:474297115
TEST=Verified that quartz starts charging when the charger is connected
via the servov4.1 to the C0 port.
TEST=Verified that quartz starts charging when the charger is directly
connected to the C0 port.
TEST=Verified that the battery is charging by checking the battery
State of charge after 20-30 mins of charging.
Change-Id: Ie5e0d980780daa0adeee4e6a3e3525eb2616a29f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When the system is in a low-power boot state or early charging mode,
it is necessary to enable charging even when a debug access port
is connected. This ensures that developers can charge the
device while using the servov4.1 with the charger.
This patch updates the charging configuration to enable the debug
access sink by writing to the TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG
register.
BUG=b:474297115
TEST=Build Google/quartz
Change-Id: I155b071e678c8bc0ff0d719ac924b5026b21b37a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91077
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add CONFIG_LP_DEFCONFIG_OVERRIDE_X64 flag to select default 64-bit
config file in payloads/libpayload/configs directory.
This is used in standalone environment. The existing libpayload
deconfig file is for boards with 32-bit format and deconfig_64
file is added for 64-bit without adding specific
board.[board name] file in libpayload.
BUG=none
TEST=Build with this new flag and check that the libpayload and
depthcharge.elf are built in 64-bit format.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84107
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483588481
TEST=build brox coreboot image
Change-Id: I9f8715311c976e92049ff3058920039c0d38ba3a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483762467
TEST=build nissa coreboot image
Change-Id: I919f92b782905ea9184203804f5ea095e37e9893
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
moxie.
Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This is a reland of
commit c4be70f6ff ("commonlib/list: Support circular list").
In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.
To support that use case, add an internal helper function _list_init()
to initialize the list as a circular one with a placeholder head node.
_list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.
Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.
Add a new test case to test iterating over an empty list.
Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00
("include/list.h: Add support for GCC9+") for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.
Change-Id: Idc22887cce71284c9028dce10eeef9cc16669028
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90962
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update the logo_bottom_margin for all fatcat variants from 100px to
200px. This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.
Modified variants:
- fatcat
- felino
- francka
- kinmen
- lapis
- moonstone
- ruby
Change-Id: Ia0f446768f1b0b13c09873176f79ed4418f28aa2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91155
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for dynamic text scaling based on the display resolution
to ensure bootsplash text remains legible on high-density panels.
Key changes:
- Implement get_resolution_scale() to determine a scaling factor (1x,
2x, or 3x) based on the panel's major dimension (HD, QHD, or 4K).
- Update draw_char() to render glyphs as scaled blocks, repeating each
font pixel across a square of the calculated scale factor.
- Apply the scaling factor to all text layout calculations, including
kerning, character advance, and total string dimensions.
- Ensure anti-aliasing (alpha blending) is correctly applied to each
individual pixel within the scaled blocks.
Change-Id: I8b22019ddaa46f1a24f38d565d946bb28a213791
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
