drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver which enables basic TBT support for the Alpine Ridge, Titan Ridge, and Maple Ridge discrete Thunderbolt controllers. This driver will initially be used on the Lenovo T480/T480s and System76 RPL-HX platform boards. Ref: edk2-platforms KabylakeOpenBoardPkg reference implementation Ref: Titan Ridge BIOS Implementation Guide v1.4 Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75286 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Soller
Matt DeVillier
parent
5db15609a7
commit
5d084f533f
5 changed files with 345 additions and 0 deletions
9
src/drivers/intel/dtbt/Kconfig
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9
src/drivers/intel/dtbt/Kconfig
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config DRIVERS_INTEL_DTBT
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def_bool n
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help
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Enable support for discrete Thunderbolt controllers (Alpine Ridge,
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Titan Ridge, and Maple Ridge). Provides device initialization and ACPI
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_DSD/opregion for S3 sleep support. Mainboards must call \TBTS from
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their MPTS so TBT is prepared before sleep.
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Note: Only a single TBT bridge device is currently supported.
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3
src/drivers/intel/dtbt/Makefile.mk
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3
src/drivers/intel/dtbt/Makefile.mk
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# SPDX-License-Identifier: GPL-2.0-only
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ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c
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8
src/drivers/intel/dtbt/chip.h
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8
src/drivers/intel/dtbt/chip.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
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#define _DRIVERS_INTEL_DTBT_CHIP_H_
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struct drivers_intel_dtbt_config {};
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#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */
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247
src/drivers/intel/dtbt/dtbt.c
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247
src/drivers/intel/dtbt/dtbt.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include <timer.h>
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#include "chip.h"
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#include "dtbt.h"
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/* Returns true on success, false on timeout or TBT2PCIE Error field non-zero */
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static bool dtbt_cmd(struct device *dev, u8 command, u32 data, u32 timeout)
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{
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u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
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u32 status;
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u8 error;
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printk(BIOS_SPEW, "dTBT send command 0x%x\n", command);
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/* Send command */
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pci_write_config32(dev, PCIE2TBT, reg);
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/* Wait for Done bit */
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if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
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printk(BIOS_ERR, "dTBT command 0x%x send timeout, status 0x%x\n", command, status);
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return false;
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}
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/* Check Error field (bits 15:12) */
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error = (status & TBT2PCIE_ERROR_MASK) >> 12;
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if (error != TBT2PCIE_ERROR_SUCCESS) {
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printk(BIOS_ERR, "dTBT command 0x%x failed, TBT2PCIE Error 0x%x (status 0x%x)\n",
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command, error, status);
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pci_write_config32(dev, PCIE2TBT, 0);
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return false;
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}
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/* Clear valid bit */
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pci_write_config32(dev, PCIE2TBT, 0);
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/* Wait for done bit to be cleared */
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if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
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printk(BIOS_ERR, "dTBT command 0x%x clear valid bit timeout, status 0x%x\n",
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command, status);
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return false;
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}
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return true;
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}
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static void dtbt_write_dsd(void)
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{
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struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
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acpi_device_add_hotplug_support_in_d3(dsd);
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acpi_device_add_external_facing_port(dsd);
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acpi_dp_write(dsd);
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}
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static void dtbt_write_opregion(void)
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{
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const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0x1000);
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const struct fieldlist fieldlist[] = {
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FIELDLIST_OFFSET(TBT2PCIE),
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FIELDLIST_NAMESTR("TB2P", 32),
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FIELDLIST_OFFSET(PCIE2TBT),
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FIELDLIST_NAMESTR("P2TB", 32),
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};
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acpigen_write_opregion(&opregion);
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acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
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FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
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}
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/*
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* Generated ASL:
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*
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* Scope (\_SB.PCI0.RPxx)
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* {
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* _DSD (Package () { ... hotplug support, external facing port ... })
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* Device (DTBT)
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* {
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* Name (_ADR, 0)
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* OperationRegion (PXCS, PCI_Config, 0, 0x1000)
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* Field (PXCS, DWordAcc, NoLock, Preserve)
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* {
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* Offset (0x2A40),
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* TB2P, 32,
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* Offset (0),
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* P2TB, 32,
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* }
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* Method (PTS, 0, Serialized)
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* {
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* Debug = "dTBT prepare to sleep"
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* Store (0x06, P2TB)
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* Debug = TB2P
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* Store (0, P2TB)
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* Debug = TB2P
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* }
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* }
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* }
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* Scope (\)
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* {
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* Method (TBTS, 0)
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* {
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* \_SB.PCI0.RPxx.DTBT.PTS ()
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* }
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* }
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*/
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static void dtbt_fill_ssdt(const struct device *dev)
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{
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/* We only want to create a single ACPI device in the SSDT */
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static bool ssdt_done;
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struct bus *bus;
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struct device *parent;
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const char *parent_scope;
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const char *dev_name = acpi_device_name(dev);
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if (ssdt_done)
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return;
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bus = dev->upstream;
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if (!bus) {
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printk(BIOS_ERR, "dTBT bus invalid\n");
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return;
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}
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parent = bus->dev;
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if (!parent || !is_pci(parent)) {
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printk(BIOS_ERR, "dTBT parent invalid\n");
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return;
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}
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parent_scope = acpi_device_path(parent);
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if (!parent_scope) {
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printk(BIOS_ERR, "dTBT parent scope not valid\n");
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return;
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}
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/* Scope */
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acpigen_write_scope(parent_scope);
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dtbt_write_dsd();
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/* Device */
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acpigen_write_device(dev_name);
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acpigen_write_name_integer("_ADR", 0);
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dtbt_write_opregion();
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/* PTS Method */
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acpigen_write_method_serialized("PTS", 0);
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acpigen_write_debug_string("dTBT prepare to sleep");
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acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
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acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
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acpigen_write_debug_namestr("TB2P");
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acpigen_write_store_int_to_namestr(0, "P2TB");
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acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
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acpigen_write_debug_namestr("TB2P");
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acpigen_write_method_end();
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acpigen_write_device_end();
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acpigen_write_scope_end();
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/* \.TBTS Method: mainboard must call this from MPTS/_PTS */
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acpigen_write_scope("\\");
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acpigen_write_method("TBTS", 0);
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acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
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acpigen_write_method_end();
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acpigen_write_scope_end();
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printk(BIOS_INFO, "%s.%s %s\n", parent_scope, dev_name, dev_path(dev));
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ssdt_done = true;
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}
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static const char *dtbt_acpi_name(const struct device *dev)
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{
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return "DTBT";
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}
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static void dtbt_enable(struct device *dev)
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{
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/* Only enable the primary bridge device (device 0, function 0) */
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if (!is_dev_enabled(dev) || dev->path.pci.devfn != 0)
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return;
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printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
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/* Set security level (Table 37/428); failure aborts enable */
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// XXX: Recommendation is to set SL1 ("User Authorization")
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printk(BIOS_DEBUG, "dTBT set security level SL0\n");
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if (!dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, SEC_LEVEL_NONE, MBOX_TIMEOUT_MS)) {
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printk(BIOS_ERR, "dTBT Set_Security_Level failed, aborting enable\n");
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return;
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}
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if (acpi_is_wakeup_s3()) {
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printk(BIOS_DEBUG, "dTBT SX exit\n");
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if (!dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, MBOX_TIMEOUT_MS))
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printk(BIOS_ERR, "dTBT Sx_Exit_TBT_Connected failed\n");
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if (pci_read_config32(dev, TBT2PCIE) == 0xffffffff)
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printk(BIOS_ERR, "dTBT S3 resume failure.\n");
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} else {
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printk(BIOS_DEBUG, "dTBT set boot on\n");
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if (dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, MBOX_TIMEOUT_MS)) {
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printk(BIOS_DEBUG, "dTBT set USB on\n");
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dtbt_cmd(dev, PCIE2TBT_USB_ON, 0, MBOX_TIMEOUT_MS);
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} else {
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printk(BIOS_ERR, "dTBT BOOT_ON failed, skipping USB_ON\n");
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}
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}
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}
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static struct device_operations dtbt_device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.acpi_fill_ssdt = dtbt_fill_ssdt,
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.acpi_name = dtbt_acpi_name,
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.scan_bus = pciexp_scan_bridge,
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.reset_bus = pci_bus_reset,
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.enable = dtbt_enable
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};
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/* We only want to match the bridge devices */
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static const unsigned short pci_device_ids[] = {
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AR_2C_BRG,
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AR_4C_BRG,
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AR_LP_BRG,
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AR_4C_C0_BRG,
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AR_2C_C0_BRG,
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TR_2C_BRG,
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TR_4C_BRG,
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TR_DD_BRG,
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MR_2C_BRG,
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MR_4C_BRG,
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0
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};
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static const struct pci_driver intel_dtbt_driver __pci_driver = {
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.ops = &dtbt_device_ops,
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.vendor = PCI_VID_INTEL,
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.devices = pci_device_ids,
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};
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struct chip_operations drivers_intel_dtbt_ops = {
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.name = "Intel Discrete Thunderbolt",
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};
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78
src/drivers/intel/dtbt/dtbt.h
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78
src/drivers/intel/dtbt/dtbt.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DRIVERS_INTEL_DTBT_H_
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#define _DRIVERS_INTEL_DTBT_H_
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/* Alpine Ridge device IDs */
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#define AR_2C_NHI 0x1575
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#define AR_2C_BRG 0x1576
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#define AR_2C_USB 0x15B5
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#define AR_4C_NHI 0x1577
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#define AR_4C_BRG 0x1578
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#define AR_4C_USB 0x15B6
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#define AR_LP_NHI 0x15BF
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#define AR_LP_BRG 0x15C0
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#define AR_LP_USB 0x15C1
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#define AR_4C_C0_NHI 0x15D2
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#define AR_4C_C0_BRG 0x15D3
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#define AR_4C_C0_USB 0x15D4
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#define AR_2C_C0_NHI 0x15D9
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#define AR_2C_C0_BRG 0x15DA
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#define AR_2C_C0_USB 0x15DB
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/* Titan Ridge device IDs */
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#define TR_2C_BRG 0x15E7
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#define TR_2C_NHI 0x15E8
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#define TR_2C_USB 0x15E9
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#define TR_4C_BRG 0x15EA
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#define TR_4C_NHI 0x15EB
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#define TR_4C_USB 0x15EC
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#define TR_DD_BRG 0x15EF
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#define TR_DD_USB 0x15F0
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/* Maple Ridge device IDs */
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#define MR_2C_BRG 0x1133
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#define MR_2C_NHI 0x1134
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#define MR_2C_USB 0x1135
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#define MR_4C_BRG 0x1136
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#define MR_4C_NHI 0x1137
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#define MR_4C_USB 0x1138
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/* Security Levels */
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#define SEC_LEVEL_NONE 0
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#define SEC_LEVEL_USER 1
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#define SEC_LEVEL_AUTH 2
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#define SEC_LEVEL_DP_ONLY 3
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#define PCIE2TBT 0x54C
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#define PCIE2TBT_VALID BIT(0)
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#define PCIE2TBT_GO2SX 2
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#define PCIE2TBT_GO2SX_NO_WAKE 3
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#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4
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#define PCIE2TBT_OS_UP 6
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#define PCIE2TBT_SET_SECURITY_LEVEL 8
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#define PCIE2TBT_GET_SECURITY_LEVEL 9
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#define PCIE2TBT_BOOT_ON 24
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#define PCIE2TBT_USB_ON 25
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#define PCIE2TBT_GET_ENUMERATION_METHOD 26
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#define PCIE2TBT_SET_ENUMERATION_METHOD 27
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#define PCIE2TBT_POWER_CYCLE 28
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#define PCIE2TBT_SX_START 29
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#define PCIE2TBT_ACL_BOOT 30
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#define PCIE2TBT_CONNECT_TOPOLOGY 31
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#define TBT2PCIE 0x548
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#define TBT2PCIE_DONE BIT(0)
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#define TBT2PCIE_ERROR_MASK (0xF << 12) /* bits 15:12, Table 38 */
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#define TBT2PCIE_ERROR_SUCCESS 0
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#define TBT2PCIE_ERROR_GENERAL 1
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#define TBT2PCIE_ERROR_ILLEGAL_DATA 2
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#define TBT2PCIE_ERROR_TIMEOUT 3
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// Timeout for mailbox commands unless otherwise specified.
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#define MBOX_TIMEOUT_MS 5000
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// Timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
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#define GO2SX_TIMEOUT_MS 600
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#endif /* _DRIVERS_INTEL_DTBT_H_ */
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