soc/amd/cezanne/acpi: Move SMN accessor to DSDT
Move the SMN accessor code from SSDT code to DSDT. This allows compiletime verification of the ACPI code. Change-Id: I3cddea079f3bfc37eb4e2b2f4496dce6441b289f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91184 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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3 changed files with 20 additions and 48 deletions
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@ -11,9 +11,6 @@ Scope (\_SB.PCI0.GP41) {
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Return (STAT)
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}
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External (\_SB.PCI0.GNB.SMNA, FieldUnitObj)
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External (\_SB.PCI0.GNB.SMND, FieldUnitObj)
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/* Read SMN register and store value into ACPI variable */
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Method (SMNR, 1, Serialized)
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{
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@ -15,6 +15,26 @@ Device (GNB)
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{
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Return (0x0F)
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}
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/* Add opregion to host bridge needed for ACP driver.
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*
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* This is used by an ACPI method in the ACP's ACPI code to access different mailbox
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* interfaces in the hardware. Some ACP drivers will use that to both notify the PSP
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* that the DSP firmware has been loaded, so that the PSP can validate the firmware
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* and set the qualifier bit to enable running it, and to configure the ACP's clock
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* source.
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*
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* As this SMN access is not arbitrated and there may be other drivers or parts of
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* the firmware attempting to use the SMN access register pair, there is a risk of
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* conflict / incorrect data, but given the frequency and duration of accesses, the
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* risk is deemed to be quite low.
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*/
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OperationRegion (PSMN, PCI_Config, 0x00, 0x100)
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Field(PSMN, AnyAcc, NoLock, Preserve) {
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Offset (0xB8),
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SMNA, 32,
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SMND, 32,
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}
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}
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/* PCIe GPP */
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@ -59,51 +59,6 @@ static void root_complex_fill_ssdt(const struct device *device)
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{
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if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
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acipgen_dptci();
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/* Add ACPI device, opregion to host bridge needed for ACP driver.
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*
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* This is used by an ACPI method in the ACP's ACPI code to access different mailbox
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* interfaces in th hardware. Some ACP drivers will use that to both notify the PSP
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* that the DSP firmware has been loaded, so that the PSP can validate the firmware
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* and set the qualifier bit to enable running it, and to configure the ACP's clock
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* source.
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*
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* As this SMN access is not arbitrated and there may be other drivers or parts of
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* the firmware attempting to use the SMN access register pair, there is a risk of
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* conflict / incorrect data, but given the frequency and duration of accesses, the
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* risk is deemed to be quite low.
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*
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* Scope (\_SB.PCI0)
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* {
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* Device (GNB)
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* {
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* Name (_ADR, 0x0000000000000000)
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* Method (_STA, 0, NotSerialized)
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* {
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* Return (0x0F)
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* }
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* }
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* }
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* Scope (\_SB.PCI0.GNB)
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* {
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* OperationRegion(SMN, SystemMemory , 0xF80000B8, 0x8)
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* Field(SMN, AnyAcc, NoLock, Preserve) {
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* SMNA, 32,
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* SMND, 32,
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* }
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* }
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*/
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acpigen_write_scope(acpi_device_path(device));
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struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY,
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CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8);
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acpigen_write_opregion(&opreg);
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static const struct fieldlist list[] = {
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FIELDLIST_NAMESTR("SMNA", 32),
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FIELDLIST_NAMESTR("SMND", 32),
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};
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acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
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FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
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acpigen_write_scope_end();
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}
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static const char *gnb_acpi_name(const struct device *dev)
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