Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.
Change-Id: I7da5cf493a676ea106ab94fcb377bc8a29b72990
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This pins aren't connected to anything so adjust them accordingly.
Change-Id: I906e3b555e7ae802f6c14285ad8a5b98f43b2f36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable the High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.
Change-Id: I6fd44b40a635bc6bb9404978493761823088b0fa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Display-Alt Mode doesn't require HPD to be set here, so remove it.
Change-Id: I6e03c481584ff2b0bbb06d1d21f31fd0db4ecb27
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86915
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Deselect this so that a local copy of PR3 can be used.
Change-Id: I7efe35457186bca43af3e5b7557cbd3be6cecbb7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86913
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Leave the rcomp config empty so that 0's are passed to FSP; this
allows FSP to figure out the correct settings to use.
Change-Id: Id7d44984c5ecfd0307d207d997248e88e1bd6eb4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The default for DQS interleaving is 0, so don't set it to 0.
Change-Id: I5f828aa3a28947c2f88eaf36cc7bc8ad68812cb2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
`ddr5_spd_info` is a better name for DDR5 memory parameters.
Change-Id: If54718592950164569fccee6e8b7d53803310de0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This enables the utility crossystem to access WP GPIO.
BUG=b:399511940
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: Ided919920dff74c49ce2f718f845ae5a1117a89b
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
According the schematic to correct PCIe RP 11 for WIFI7.
BUG=b:388117663
TEST=build pass and insure WLAN function work properly
Change-Id: I84e9fc707c23099d7cd7ea2d8acde1043325f06b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Enable PCIE port 7 using clk 3 for RTL8111H Ethernet.
BUG=b:388117663
TEST=build pass and insure LAN function work properly
Change-Id: I60c30f207aa92ba9f52da0b95b647307a73e9d13
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit c476c4d5b9.
Reason for revert: Previously in CB:85799, we added a 0.5ms delay as a
workaround to solve the boot hang issue of non-serial firmware. Now that
the root cause has been identified and fixed in CB:86859, we can revert
the workaround.
Original change's description:
CB:85799, commit c476c4d5b9 ("soc/mediatek/mt8196: Delay 0.5ms after
enabling PMIF SPMI SW interface")
BRANCH=rauru
BUG=b:341054056
TEST=Build pass.
Change-Id: I0abdcae95924c4d3197496c14d20502b08938d76
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Currently, we don't explicitly disable the PMIF and SPMI resets after
the reset is completed, causing them to remain asserted for
approximately 0.5ms. That would cause the DUT to hang during PMIF
initialization (pmif_spmi_init) when using non-serial firmware.
To fix this issue, explicitly disable the PMIF and SPMI resets
immediately after the reset.
BRANCH=rauru
BUG=b:341054056
TEST=Build pass, non-serial firmware boot ok.
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ic903ddd893470cd46dbfed9c3faa9c2a9e50c904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86859
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meliks uses GPP_E7 to determine the channel count of the RAM chip in
romstage, move its configuration to early_gpio_table from
override_gpio_table to be ready to use at that moment.
And early stage meliks boards didn't implement the GPP_E7 strap but
leaved it as NC. All of them used two channel ram chip, so add DN_20K
for them not to disable any memory channel. Otherwise, they might not
be able to boot since memory training will be failed due to the
incorrect memory channel information.
BUG=None
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot
Change-Id: Icf71c3a1f24d3dcbff6ba5e646e9f805144add71
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86908
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch corrects spacing around assignment operators in the
`fill_blt_buffer` to comply with coding style guidelines, specifically
within the BMP color translation logic for 1/4/8/24/32-bit images.
Change-Id: Ia243d11568ec4c3d1108ff60289743919394aa32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86860
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/guybrush (nipperkin), verify FPR does
not show up as unknown device under Device Manager.
Change-Id: I3eac631aebb26ec1c375b436e088be522d659338
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86847
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces new board ID definitions for PTL-P and GCS in the
PTLRVP mainboard code. The changes involve updating the `romstage.c` and
`memory.c` files to handle these new board IDs, ensuring that memory
configuration is correctly initialized based on the detected board
type.
Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PSP_SOFTFUSE_BITs were probably copy&pasted during initial
SoC bringup and need to be adjusted:
* Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang.
* Drop PSP_SOFTFUSE_BIT BIT34 as it's not required.
This also moves coreboot closer to the UEFI reference firmware.
Document #55758 Rev. 2.04
TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS.
Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Don't set this, so FSP will use the default auto setting, which
behaves better with various memory sizes.
Change-Id: I4d0bfd19af08ec127065f7ad5aaa51cb7e0ca2ac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86905
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.
Change-Id: Ifcd107f0c889fc5210bdb8578d1df27b9e4414ff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86903
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce support for an IPC mailbox interface that lets the OS
exchange commands and responses with the Power Management Controller
(PMC) when needed.
Change-Id: I31ba44dc6fb848dda94321e1c17e64ddf6abe637
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86902
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all the controlling GPIOs to IOSTANDBY_IGNORE to
ensure they work in S3.
Change-Id: I1b34793a6437d2e489fca90be1f5d3e13ec7d559
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Don't configure the eSPI GPIOs as they are configured automatically on
reset.
Change-Id: Icdd6e916571bad33404fa91a1e288e0a18d7778b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.
Change-Id: Ibee64ccd9f21f33b764aacc4f97404ba56e5102e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the PMC alert and SML Clock/Data pins to IOSTANDBY_IGNORE to ensure
that they're still operational in S3.
Change-Id: I1dd7a9410211c50cc171645f6db82b15c52ff7ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
GPP_C03 and GPP_C04 are not used for the StarBook, so disconnect them.
Change-Id: I5e2c3da1198f064800f6f897583e507b6ae8a656
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86897
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Display-Alt Mode doesn't require HPD to be set here, so remove it.
Change-Id: I2a22519dcf87e77fabefe0d2a392808d9b449872
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DDC so that GOP can read the backlight brightness from EDID. This
avoids FSP repeatedly trying and failing to read it, and also stops the
backlight brightness not being restored correctly in Linux.
Change-Id: Icd292ee175a14799fe08c0989ca3fdccd5ccc123
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The table included 3 entries for GPP_F00, so adjust them to the
correct pads.
Change-Id: Ic8d3a2e742f01231d1a4b777879da0b310085efe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86894
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 07dd73c921.
Jasperlake FSP does not properly support the crashlog feature, and
enabling it results in several issues (increased boot time, issues
with USB device detection).
Change-Id: I5598b40321b3ca15a48ac6eff64a85323d55939d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Jasperlake FSP does not properly support the crashlog fearture, and
selecting this option significantly impacts boot time negatively by an
order of magnitude (~10s vs ~1s) and breaks USB detection in edk2
payload; inability to properly enumerate USB devices is almost
certainly the cause of the increased boot time.
TEST=build/boot google/maglia, verify boot time normal (~1s) and USB
detection working as expected with multiple USB devices connected.
Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84359
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Use the newly-created ACPI device in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Ie4d9a480152fabb93d784b338c2846feba874f4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Id7b68e7c5ed554639dc14e837e311552c3ff92f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: I3a4b122b206cb1fc98e693973f2aeb28e8b2ff22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86814
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces power consumption so enable it. For example,
`starbook/adl_n` idles at 5.16W with this disabled, but 4.6W with
it enabled.
Change-Id: I5b6fd4853aba0dd4e9f9f45be4b43efff375dfad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up Energy Efficient Turbo to devicetree so it can be configured.
The default value of 0 will ensure this doesn't change existing boards.
Change-Id: I58a9877371ec66e71cee15aced2413a282416b5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86855
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be set to the opposite of lockdown_by_fsp.
Change-Id: I9e3c8f03ca14d2cb28c3f2f9bd74618d81e53d2c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86854
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCO SMI handler clears the watchdog timeout flag unconditionally.
Since the system is only rebooted if the flag is already set and the
watchdog timer expires again, this means that the reboot never occurs.
This change preserves the timeout flag if CONFIG_ACPI_WDAT_WDT is
enabled, otherwise the behavior remains unchanged.
TEST=Build CB with CONFIG_ACPI_WDAT_WDT=y and
CONFIG_USE_PM_ACPI_TIMER=y, trigger the watchdog under Linux
with "wdctl -s 5 && cat > /dev/watchdog" and wait approximately 10
seconds (two watchdog periods) for the watchdog to reboot the system.
Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84875
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
FW Init Complete is a prerequisite for sending the FW FEATURE SHIPMENT
TIME STATE OVERRIDE message. Unfortunately, on some platforms such as
Lenovo ThinkCentre M700 Tiny, it takes too long for the flag to be set,
so enabling PTT fails.
Wait up to 5 seconds for the FW Init Complete to be set instead of
failing immediately.
On M700 Tiny with debug level set to ERROR, we have to wait nearly 2
seconds:
[EMERG] HECI: CSE took 1900 ms to complete FW init
Because FW Init Complete is not required for getting the current feature
enablement state, only for setting, move the FW Init Complete check to
after we've determined if we actually need to change the state. This
avoids needlessly increasing boot time.
Reference: Intel ME 11.x BIOS Specification, #549522, section 6.3.15
Change-Id: Ib6de170f3f998273bec437848faa49652f013f45
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84862
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been observed that at least on some M700 Tiny boards, CLKREQ
signals aren't wired as per the schematic. Disable them and configure
their pads as per original Lenovo UEFI.
This change fixes Wi-Fi card detection on M700 Tiny.
TEST=Boot M700 Tiny with AX200 card in Wi-Fi card slot and boot to
Windows 10. Check that Wi-Fi works correctly.
Change-Id: I5b26937cd4a6937b516304fefad9186b9e1cdc76
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84813
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coolstar's Windows drivers require the IOM device to be visible to the
OS, so add a Kconfig to control this, which mainboards will select in
subsequent patches.
TEST=build/boot Win11 on rex/screebo, verify USB4 drivers functional.
Change-Id: I00ef9703179d87b7b476ef18d8d02fcafa9e14ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86792
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 'ctags' target.
we can see that 'make help' says
...
ctags / ctags-project ...
...
but, Makefile have only 'ctags-project' target.
Change-Id: Ie554892bcb072d773babf745d7756630327d2975
Signed-off-by: melongmelong <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85936
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ] EnableTcssCovTypeA[0]= 0x00000000
[SPEW ] MappingPchXhciUsbA[0]= 0x00000000
[SPEW ] EnableTcssCovTypeA[1]= 0x00000001
[SPEW ] MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf
BUG=b:400809281
TEST=Able to build and boot google/Riven
Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly-created ACPI devices in common/acpi, to align with other
client SoCs.
Change-Id: Icc5da0b820101b3c651ed59a47aeab37440a6996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Iabd9dec2f6838c1dc4b1cad924ceb62c992f89c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
