Refactor Kconfig dependency by moving the selection of Secure OS
(TrustZone/TEE) features from the mainboard configuration to the
specific SoC configuration layer.
The selections for `ARM64_USE_SECURE_OS` and
`ARM64_USE_SECURE_OS_PAYLOAD` are moved from `BOARD_GOOGLE_BLUEY_COMMON`
to `SOC_QUALCOMM_HAMOA`.
This ensures that the Secure OS requirements are correctly associated
with the Hamoa chipset family itself, leading to better modularity and
future compatibility for Hamoa-based platforms.
Crucially, this change allows for precise control of the Secure OS
(BL32 firmware) applicability. By selecting the feature only within
`SOC_QUALCOMM_HAMOA`, we can ensure that platforms utilizing the
"Purwa SoC" family (which currently does not have a ready/available
SecureOS) automatically avoid the selection of these Kconfig options.
The change is verified by ensuring the QTEE (SecureOS) feature is
disabled for platforms using the Purwa SoC, specifically verified on the
google/quenbi mainboard.
BUG=b:459268465
TEST=Ensure disabling QTEE aka SecureOS feature for google/quenbi w/
Purwa SoC.
AP firmware log shows the expected path taken when SecureOS is disabled:
```
WARNING: No QTEE entry point provided by BL2 boot loader,
Booting device without QTEE initialization.
```
Change-Id: Ic82a29a4330cc6e5f99727fc40ec73b38cbbc72d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90011
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Simplify board-level Kconfig by consolidating the selection of SPI flash
drivers into the common configuration option.
Previously, individual board models explicitly selected their specific
SPI flash drivers (e.g., SPI_FLASH_MACRONIX, SPI_FLASH_WINBOND).
This patch standardizes the approach by:
1. Selecting `SPI_FLASH_INCLUDE_ALL_DRIVERS` in
`BOARD_GOOGLE_BLUEY_COMMON`.
2. Removing the redundant vendor-specific selects from
`BOARD_GOOGLE_MODEL_BLUEY`, `BOARD_GOOGLE_MODEL_QUENBI`, and
`BOARD_GOOGLE_MODEL_QUARTZ`.
This change ensures all derived board models inherit the comprehensive
set of SPI flash drivers, simplifying maintenance and improving
flexibility for multi-vendor support.
BUG=b:456953373
TEST=Able to verify that the SPI flash getting correctly probed.
Change-Id: I3eb573d0069bfc1d7caab36c9a7a2a223d81c5df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add dt_is_overlay() API to check whether the input devicetree is
actually an overlay DT. Payload will use this API when parsing an input
image which is a collection of base and overlay devicetree blobs.
BUG=b:394980221
TEST=Build firmware image for Rauru/Hylia and boot to OS. Ensure that
the API correctly identifies the base and overlay DTs.
Change-Id: I2fc54e3d9e63ebc993c8ce6a7d4a7224a9251497
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix USB 3.2 Type-A port0/1 Tx compliance failures in EA test
- De-emphasis test failed: Actual value = 0.000000 dB,
requirement: -7.0 dB <= value <= -2.1 dB
- Preshoot test failed: Actual value = 0.000000 dB,
requirement: 1.2 dB <= value <= 3.2 dB
Set Type-A USB3 port0/1 tx_de_emp to 0x4 for signal integrity
BUG=b/451560515
TEST=build FW and check Type-A
USB3 port0/port1 RX pass in EA test
Change-Id: I1a563fbc27d2dac8b57a62b7bfded73e1a6732cf
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Kconfig to enable building iPXE for EFI target, which can be
executed from EDK2. If not selected, iPXE will be built for use with
legacy BIOS. Add support to the Makefile to build the EFI target.
Change-Id: I7f247a59a65aeb18a67475d4d543f519af88aeb9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83385
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for configuring the NVMe Power Loss Notification (PLN)
GPIO before powering on the NVMe device.
The Hamoa target has the PLN signal wired to SoC GPIO 157. The voltage
level conversion circuitry between the SoC (1.2V) and NVMe (3.3V) causes
the PLN signal voltage level to vary depending on the NVMe part used.
This change configures GPIO 157 as an input with no pull resistors and
2mA drive strength to ensure proper PLN signal handling and allow the
GPIO to be used for other hardware configurations.
Changes:
- Add NVME_PLN_GPIO definition for GPIO(157)
- Add nvme_core_pln_gpio() function to configure PLN GPIO
- Update gcom_pcie_power_on_ep() to call nvme_core_pln_gpio() before
enabling NVMe power regulator
TEST=Boot the Google/Bluey board and verify NVMe device is detected
and functional
Debug logs:
Initializing NVMe controller 1e0f:000c
nvme_ctrlr_init: PCI Command register = 0x2
nvme_ctrlr_init: PCI Status register = 0x10
nvme_ctrlr_init: PCI Command after bus master enable = 0x6
iosq_sz = 11, iocq_sz = 11
nvme_wait_status: Waiting for CSTS & 0x1 == 0x0, timeout=30000 ms
nvme_ctrlr_init: Waited 100ms after controller disable
nvme_enable_controller: CSTS before enable = 0x0
nvme_enable_controller: CAP register = 0x303c03ffff
nvme_enable_controller: CAP.TO timeout = 30000 ms
nvme_enable_controller: Writing CC register = 0x460001
nvme_enable_controller: CC register readback = 0x460001
nvme_wait_status: Waiting for CSTS & 0x1 == 0x1, timeout=30000 ms
nvme_enable_controller: CSTS after enable = 0x1 (status=0)
Identified NVMe model KBG50ZNS256G KIOXIA
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
Change-Id: Icc22cfd397a0adbc051b2b1a2178aeedb7389ac0
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90037
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When updating clang to version 21.1.5, we now get the following error
when compiling the CFR code.
```
src/drivers/option/cfr.c:287:19: error: default initialization of an
object of type 'struct sm_object' with const member leaves the object uninitialized
[-Werror,-Wdefault-const-init-field-unsafe]
287 | struct sm_object sm_obj_copy;
```
In this specific case its actually not an issue, but initialize the
variable from the start to avoid the error and arguably make the code
easier to read.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib0b22e20a7482ab29d997a3e3c3bec4a1db1a4f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89958
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.
No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.
Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/
TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode
Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Allows ifittool to add FIT entries for files that are located in a
different FMAP region than the FIT table.
The region from where to source the file can be specified with -R.
If not given it defaults to using the value of the mandatory -r,
for full backwards compatibility.
Example: Tested with a custom binary with the bootblock and
corresponding FIT table in a separate region, and the microcode still
in the COREBOOT region:
λ ./ifittool -f test_ts.rom -a -n cpu_microcode_blob.bin -t 1 \
-r BOOTBLOCK \
-R COREBOOT \
-s 4
Change-Id: I7e49247f280ec118e09cf173795d7602a4c0d7f6
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89608
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the payload (depthcharge) is getting bigger for new features, the RW
CBFS sections for boards with 16MiB flash are not large enough.
Therefore, reduce RW_LEGACY from 1M to 512K, and increase each of
RW_SECTION_A and RW_SECTION_B by 256K.
NOTE: This is a RO/RW incompatible change, and should NEVER be
cherry-picked to firmware branches.
BUG=b:459853033
TEST=cq
BRANCH=none
Change-Id: If1b998e4ac8e5f00dee0b8afcf324c5f6bab697c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
There is no reason I can think to also pass the old object into the
constructor considering that the new objects contains the exact same
contents during that call (it's copied over a few lines above).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idd5b34134b6064c19266448b551248eb29e097fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89957
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Introduce the `USB3_PORT_TX_CFG` macro to simplify the definition of
`usb3_port_config` structures.
This macro allows platform code to easily configure the Transmit
De-emphasis (`tx_de_emp`) value for a specific USB 3.0 port (identified
by `ocpin`).
This improves readability and reduces boilerplate when tuning signal
integrity settings for different USB ports on the board.
TEST=Able to build and boot google/kinmen.
Change-Id: I42565e2c573dfcff244a81bf7bcb9749eca52c05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add ACPI power state methods (_PS0, _PS3, _S0W, _S3D) to the GFX0
device definition to fix VIDEO_TDR_FAILURE 0x116 errors when
resuming from S3 sleep under Windows on modern Intel platforms
(TGL and newer).
Windows requires these methods to properly manage GPU power states
during sleep/resume cycles. Without them, Windows cannot determine
the correct power state transitions, leading to display driver
timeouts on resume.
The methods are implemented as no-ops since integrated graphics
power is managed by the platform, but Windows needs the method
definitions to properly initialize and restore the GPU after S3
resume.
TEST=build/boot starlabs/starlite_adl, verify S3 resume from
Windows works properly without a VIDEO_TDR_FAILURE BSOD.
Change-Id: Ib3f8060dee3281c2281d4e719be9aff9e0239b49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90013
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently we may return an undefined pointer called
`none_driver_config` since stack variables are not by default
initialized to 0/NULL.
This also causes an issue when updating to a clang version 21.1.5 from
version 18.1.8, since it complains about this very issue.
returning NULL is fine, since the macros in this file actually depend on
it to figure out where to get the config from.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b719ca9fd41409375f635b1dcddbc5796b48fe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Convert SATA controller ACPI OperationRegion and Field definitions from
static ASL code to runtime-generated acpigen code. This allows the SATA
registers (STB5, SB5, and port fields P0ER-P3PR) to be conditionally
included in ACPI tables only when the SATA controller (device 00:11.0)
is enabled in the devicetree.
Including them unconditionally when the SATA PCI device is disabled
causes Windows to BSOD (ACPI BIOS ERROR), since the OpRegion references
a non-existent device.
Changes:
- Move SATA OperationRegion generation to sata.c using acpigen APIs
- Remove static SATA fields from acpi/pci_int.asl
- Add stoneyridge_sata_ops with acpi_fill_ssdt callback
- Update chipset_st.cb and chipset_cz.cb to use stoneyridge_sata_ops
- Remove Kconfig for SoC common SATA code, since no longer used
This reduces ACPI table size when SATA is disabled and properly scopes
SATA registers to the SATA device.
TEST=boot Win11 on google/liara without a BSOD
Change-Id: I6e7a9a60e3622368eac83c36efd384c8d92c2b05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Linux kernel images from upstream tree are compressed using legacy LZ4
format and not the modern LZ4 format. Hence support legacy LZ4
compression format to decompress and boot upstream Linux kernel images.
Also add unit test case to verify the currently supported LZ4
compression format as well as legacy LZ4 compression format.
References:
* https://github.com/lz4/lz4
BUG=None
TEST=make tests/liblz4/lz4-test
[==========] tests_liblz4_lz4-test(tests): Running 4 test(s).
[ RUN ] test_lz4
[ OK ] test_lz4
[ RUN ] test_lz4_partial_decompression
[ OK ] test_lz4_partial_decompression
[ RUN ] test_legacy_lz4
[ OK ] test_legacy_lz4
[ RUN ] test_legacy_lz4_partial_decompression
[ OK ] test_legacy_lz4_partial_decompression
[==========] tests_liblz4_lz4-test(tests): 4 test(s) run.
[ PASSED ] 4 test(s).
Change-Id: I7e3d407fc313e0937fd8d327840534de60d8c625
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Configure CPU root port 1 to operate at PCIe Gen2 speed instead of
the default Gen3. This change addresses signal integrity issues on
the PCIe link that prevent reliable operation at Gen3 speeds.
TEST=Booted on mc_rpl1 and verified CPU RP1 operates at Gen2 speed
with `lspci -vv -s 01:00.0 | grep LnkSta`. Output shows
`LnkSta: Speed 5GT/s (downgraded), Width x2`
Change-Id: I35650d46d4c2ac6942b2e68a4fd23fe875bd0c10
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add PCIe speed configuration for CPU root ports in FSP-M. Previously,
only PCH root port speed could be configured via FSP-S. Since CPU root
ports are initialized in FSP-M, they require configuration during
romstage.
This change uses the pcie_speed_control_to_upd() helper (now available
in the shared header) to convert devicetree PCIE_SPEED_control values
to FSP UPD indices. The configuration respects the pciexp_speed CMOS
option override if present, otherwise uses the devicetree setting.
TEST=Booted on mc_rpl1. Configured CPU RP to different PCIe speeds
(Gen1/Gen2/Gen3) via devicetree and verified correct link speed
negotiation with lspci for each configuration.
Change-Id: If3d871f238e7f063fef01c68cc371ae72ec9642c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Include guards should cover the whole file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
The Lapis board has a Cirrus CS35L56 smart audio amplifier, which needs
board-specific firmware to work properly [1]. The OS uses the SVID/SSID
of the host PCI audio interface to know which firmware file to use.
Set the correct SVID/SSID for Lapis so that the OS can load the correct
firmware for the CS35L56.
[1]: https://www.kernel.org/doc/Documentation/sound/codecs/cs35l56.rst
BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"
Change-Id: Ie726d3d1c1a42f1961a63d62f3bb8809f6a29d29
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89978
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The console UART base address for Panther Lake is being updated from
0xfe036000 to 0xfe02c000 (as per FSP version 3272). This correction
ensures the console initializes with the correct UART base address.
TEST=Able to get FSP debug log while building google/fatcat.
Change-Id: Ic123189fb5689318a4940edcfcf206c32e3ccf26
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The option FSP_UGOP_EARLY_SIGN_OF_LIFE is not supported for the 'lapis'
and should be removed from its Kconfig selection.
BUG=b:459309919
TEST=Able to see firmware splash screen while booting google/lapis.
Change-Id: Ifcc7f4fe8658cf8d2fdada5a5de84c8ee352861a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Cosmetic fix validated on a Thinkpad T470s.
Change-Id: I7e2032a665933cb7e002a7202bcd4305dfcdbed4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
We have a hard alignment to LB_ENTRY_ALIGN (4). We check for an
alignment of 4 bytes at the beginning of each lb_record. But since it
was 8 byte aligned, it was also automatically 4 byte aligned.
It therefore wasn't detected by coreboot.
This will break payload implementations that rely on the 8 byte
alignment for this specific struct. But since lb_smmstorev2 has only
been recently updated in commit 5bf88a44e9 ("drivers/smmstore:
Support 64-bit MMIO addresses"), one can only hope that no payloads
were updated to this yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib6171b7d4bd08b8a1559833ddb048644ff082b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PcdFirstTimeWakeUpAPsBySipi controls the sequence of IPIs sent to APs
during AP wakeup in UefiCpuPkg. Since coreboot leaves APs parked in
halt loop, SIPI is not enough to wake them up. They need to go through
regular INIT-SIPI-SIPI sequence. Set PcdFirstTimeWakeUpAPsBySipi to
FALSE to cause the MP code in UEFI Payload to send INIT-SIPI-SIPI
sequence, otherwise the APs are not detected in UEFI Payload.
Additionally, after rebasing to the latest UefiCpuPkg, CpuDxe now calls
MpInitLibStartupAllCPUs() while setting up per-CPU exception stacks.
If we leave `PcdFirstTimeWakeUpAPsBySipi` at its default (TRUE), only a
SIPI is issued on the first wake attempt. The APs that coreboot parks in
an HLT loop never acknowledge that SIPI, the DXE driver trips
`ASSERT_EFI_ERROR()` and the UEFI payload reboots straight back into
coreboot. Explicitly set the PCD to FALSE so the INIT-SIPI-SIPI flow is
used and all cores report in.
before:
MpInitLib: Find 1 processors in system.
after:
MpInitLib: Find 4 processors in system.
TEST=edk2 boots cleanly on Star Labs Lite ADL (Intel N200) and
Gigabyte MZ33-AR1; DXE log shows all processors detected.
Change-Id: I299b74892a56894c3e15507b507a50bdf7e59860
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89210
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This change adds support for the TAS2563 codec in the device tree
and enables it based on the fw_config.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I924518aab5463ed49bd2341cab0104e6ed3ed14b
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
Enables correct identification of boards using tas2563 speaker amplifier
by SOF Windows drivers.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I7dd0276a44ebb9b0712589c28ac017bff1ed5b1a
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89878
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel.
This was tested on the fatcat/variants/ruby mainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I801ef13937078ca9cfcd3610b1aa8aaedbaf1cf1
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.
Default (0) means PIO, while 1 means DMA.
Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Extract PCIe RP clock configuration logic to a separate function,
following the same refactoring done for Meteor Lake in CB:89790.
Change-Id: I0abc48c066697199acfc7b77ee553e4e8c7b5119
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.
While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.
Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The slow battery charging control was split across two locations:
1. Unconditionally enabled in `romstage.c`.
2. Conditionally disabled later in `mainboard.c` for normal boot mode.
This split logic is unnecessary and can be simplified. Battery charging
should only be enabled when the system determines it needs to enter a
low-battery boot mode (`LB_BOOT_MODE_LOW_BATTERY`).
This commit refactors the control flow by:
1. Removing the unconditional `enable_slow_battery_charging()` call from
`romstage.c`.
2. Enabling `slow_battery_charging()` only within `lb_add_boot_mode()`
when the determined boot mode is low-battery.
This ensures charging is managed solely based on the determined boot
mode, confining the control logic to a single location.
BUG=b:457566143
TEST=Able to build and boot google/quenbi. Ensure charging is only
enabled in AP firmware if booted in low-battery mode.
Change-Id: I906d555b9fa4ad2581f598621ea96bda891ff47e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The USB port configuration macros (covering USB 2.0, 3.0, and TCSS) are
currently duplicated across multiple Intel SoC headers.
This patch refactors the definitions into a new, central IA common
header file. Moving these macros to a shared location eliminates
redundant code, simplifies maintenance, and ensures consistency across
platforms.
Specifically, this refactoring allows Intel Meteor Lake (MTL) and
Panther Lake (PTL) to immediately adopt the common definitions.
TEST=Able to build and boot google/kinmen.
Change-Id: I7fb1e4d100c6d72eba0e31f37aa58e6d741ceea6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89984
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add ruby project new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Micron MT62F1G32D2DS-020 WT:D
Samsung K3KL8L80EM-MGCV
BUG=b:446771934
TEST=Use part_id_gen to generate related settings
Change-Id: Ic2710e9a5e59ffecb3fd696c15b944eb58e23f0b
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89886
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Xeons implementation and the common intel implementation are identical
functionality wise so just use the common function.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Update SX9324 register settings based on tuning values from SEMTECH to
adjust the proximity sensor sensing range to support 5G LTE module.
BUG=b:445338278
TEST=Confirm P sensor function can work and check i2c register settings
on Guren by command # i2cwatch -f -y 14 0x28
Signed-off-by: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Change-Id: Ic5e8fe1c67dcdfcfc9a4657b9d859a3b71239858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Retrieve SVID/SSID via devicetree and program to HDA device
BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"
Change-Id: I6bf4b5f2cbce69429daabce83ab11c13272194f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89983
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.
To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.
Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
`cfg[i].clk_req` is a `uint8_t` so use `%u` instead of `%d`.
Change-Id: I6c7a6ecbd2f5b917d44923d0ad6cb331d9bb054c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89789
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.
Mainboards can now declare a simple override table mapping option
names to new default values:
const struct cfr_default_override mb_cfr_overrides[] = {
CFR_OVERRIDE_BOOL("s0ix_enable", false),
CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
CFR_OVERRIDE_END
};
The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.
Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SKUs of pujjoquince have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:454252968
TEST=Build FW and checking SD card reader register is correct like
printk(BIOS_INFO, "Luca_0x%x: %x\n", ltr_cap + PCI_LTR_MAX_NOSNOOP,
pci_read_config16(dev, 0x236));.
Change-Id: Ib04a419b86213b6ffef25d7f6f64668abaf36801
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89890
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In the arm64 exception handler in libpayload, we use the banked
exception stack pointer (SP_EL2, as opposed to the normal SP_EL0) not as
a normal stack pointer, but simply as a pointer to the exception_state
struct. This makes it easy to dump all registers into that struct on
context switch. We then immediately switch back to SP_EL0.
Yet, even though it is not really a stack for us, the aarch64
architecture still requires that SP_EL2 is 16 byte aligned at function
boundaries. If the exception_state struct is not thus aligned,
exceptions are broken. (I don't know why nobody ever hit this before,
but I hit it now while trying to pull in zstd code. I guess we just
don't have unaligned BSS entries that often and simply got lucky for a
while. 3 hours wasted on debugging. :( )
Change-Id: Id19184656fb9da68fe4bfdbc240c0c25b9d24cd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This chang adds the necessary configuration for ILITEK touchscreen
(ILIT2901) device. The relevant parameters are from the manufacturer's
email dated October 13th. Furthermore, adding fw_config THC_ILITEK
ensures that the touch functionality of both touchscreens is normal.
BUG=b:455442712
TEST=emerge-fatcat coreboot and chromeos-bootimage,
flash to DUT, ilitek touchscreen can be found by `getevent`,
and no wake-up functionality when the DUT is in sleep mode.
Change-Id: I7611c7b1e1364e48ae87a0d91ad3106130ccc586
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add FW_CONFIG probe based on lapis boxster of below devices:
touchpad, audio and touchscreen.
BUG=b:456579786
TEST=Boot to OS and verify the touch and audio device are set
based on fw_config
Change-Id: I6943a0cd6304a6d92481d2904bfa5082944ffd70
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89939
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
