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mb/google/var/fatcat/lapis: Modify type-A USB3 port0/1 tx_de_emp

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Fix USB 3.2 Type-A port0/1 Tx compliance failures in EA test
- De-emphasis test failed: Actual value = 0.000000 dB,
requirement: -7.0 dB <= value <= -2.1 dB
- Preshoot test failed: Actual value = 0.000000 dB,
requirement: 1.2 dB <= value <= 3.2 dB
Set Type-A USB3 port0/1 tx_de_emp to 0x4 for signal integrity

BUG=b/451560515
TEST=build FW and check Type-A
USB3 port0/port1 RX pass in EA test

Change-Id: I1a563fbc27d2dac8b57a62b7bfded73e1a6732cf
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tongtong Pan 2025-11-12 14:56:20 +08:00 • committed by Subrata Banik
commit 0416ac9829
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/fatcat/variants/lapis/overridetree.cb
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@ -80,8 +80,8 @@ chip soc/intel/pantherlake
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #1 (MB)/
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 (DB)/
register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB)/
register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB)/
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"