mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2 speed

Configure CPU root port 1 to operate at PCIe Gen2 speed instead of
the default Gen3. This change addresses signal integrity issues on
the PCIe link that prevent reliable operation at Gen3 speeds.

TEST=Booted on mc_rpl1 and verified CPU RP1 operates at Gen2 speed
with `lspci -vv -s 01:00.0 | grep LnkSta`. Output shows
`LnkSta: Speed 5GT/s (downgraded), Width x2`

Change-Id: I35650d46d4c2ac6942b2e68a4fd23fe875bd0c10
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb

@@ -75,6 +75,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.flags = PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_pcie_speed = SPEED_GEN2,
 			}"
 		end
 		device ref pcie4_1 on