The alias isn't referenced anywhere, so remove it in preparation of
adding a chipset devicetree using the same alias in a subsequent patch.
TEST=build google/dedede (dexi)
Change-Id: I0745eab9b0947b790f64383549e205bd906ba555
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90896
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RAM ID for K3KL8L80CM-MGCT. And importing a single RAM device,
so use mb_get_channel_disable_mask to distinguish it.
BUG=b/468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.
Change-Id: Idc1e890ab826ec008031f54e0fc445fa5ee62978
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change adds support for I2S codec in the device tree and enables
it based on the fw_config based on WCL_GPIO_Implementation Rev0p7.
RDC Doc no: 836031
BUG=b:465888555
TEST=Boot on google ocelot board and Enable I2C Codec for Audio.
Check Mic and Speaker functionality
Change-Id: I51fb849bf365108be1ff59d65069329e5fd08824
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90427
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Checked with the SED team and confirmed that the HID name needs
to be changed to "GT 7936".
BUG=b:478990702
BRANCH=none
TEST=Build the image and boot to the OS, then check that
the touchscreen HID name has changed to "GT 7936"
in the diagnostics app.
Change-Id: Id0ce797b121c4a7bcf7bf15bfc81e9b079ebb3c4
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90941
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
TEST=Boot glinda based mainboard and see Type 19 and 20 entries using
dmidecode tool.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9a0abab9a5324f83659180a3842a8b5d9c6b3820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The current CBMEM top is situated at the base of 'dram_xbl_log'
(0x81A00000), leaving only 4.4MB of usable memory below it. This
space has become insufficient for the growing size requirements of
the coreboot configuration tables and boot services.
Relocate the CBMEM top to the base of the PIL region (0x866C0000).
This move increases the available contiguous memory for CBMEM
allocation from 4.4MB to 7.3MB, ensuring sufficient headroom for
the tables and reducing fragmentation for the OS and runtime services.
Changes:
- Update cbmem_top_chipset() to return _dram_pil as the new boundary.
- Update memlayout.ld documentation to reflect CBMEM's new position
directly below the PIL region.
TEST=Verified CBMEM initialization on Bluey; confirmed coreboot
tables are correctly allocated at the new high-memory boundary and
no overlaps occur with reserved regions.
Change-Id: I26d95b952634ce06ed2171c75bc6a129c15ec3b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
The previous 12MB WP_RO size is an invalid range for the SPI controller.
Hardware write-protection requires power-of-two or specific
block-aligned boundaries, making 12MB unenforceable.
Reduce WP_RO to 8MB to ensure hardware WP can be correctly enabled.
The reclaimed space is assigned to RW_UNUSED.
BUG=b:479139462
TEST=Build and verify FMAP layout on Bluey; confirm hardware WP
enforcement.
Change-Id: I4515eab3941913942fc5994e7094986e2edbd6d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90952
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit c4be70f6ff.
Reason for revert: The CL caused a hang in Depthcharge on
Google/Quartz.
BUG=b:479143030
TEST=Verify boot on Google/Quartz.
Change-Id: I38087d0b2dd218dfb32a02c343b199708bb47d49
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.
To support that use case and make the change backward compatible, add a
helper list_init() function to initialize the list as a circular linked
list. list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.
Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.
Add a new test case to test iterating over an empty list.
Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00
("include/list.h: Add support for GCC9+) for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.
Change-Id: I8451f711d4e522e239c241b3943e00070896dec9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90799
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the 4K alignment for PRERAM_DMA_COHERENT and adjust the post-RAM
memory layout to ensure page-aligned boundaries.
- Shift PRERAM_DMA_COHERENT from 0x14857000 to 0x14858000. This 4K
alignment is required for the MMU to correctly apply uncached
attributes without overlapping adjacent regions.
- Increase POSTRAM_STACK from 16K to 32K to provide more headroom
for complex ramstage operations.
- Shift and expand POSTRAM_DMA_COHERENT to 0x8000C000 (16K). This
ensures the coherent region starts on a 4K boundary after the
expanded stack, preventing cache coherency issues.
This alignment fix resolves intermittent SPI DMA failures and hash
mismatches observed when the DMA engine was handed unaligned
buffer addresses.
BUG=b:477842629
TEST=Verified successful boot on Bluey; confirmed SPI read
stability and vboot verification pass.
Change-Id: Ic5f813e4722d732c122186897abf845e4060db37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90888
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boost the SPI bus clock frequency from 50MHz to 75MHz in the
bootblock early initialization.
This increase reduces the latency for loading subsequent stages
(romstage/ramstage) from the SPI flash. Since the QSPI core
can now be configured to 300MHz, this 75MHz bus speed
maintains a stable 1:4 integer divider ratio, ensuring optimal
signal integrity and timing margins for the flash interface.
BUG=b:478226455
TEST=Verified successful boot on Bluey. Observed a reduction (10ms)
in 'read SPI' duration in the console logs and confirmed that the
vboot hash verification passes consistently.
Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add a new frequency entry to the QSPI core clock configuration table
to support 75MHz (75 * 4 = 300MHz).
This is achieved by using the GPLL0 600MHz source with a divisor of 2.
Providing a 300MHz core clock allows for more granular control over
the physical bus speed (SCK). Specifically, it enables a stable 75MHz
SPI bus frequency via a clean 1/4 divider, which is an optimization
target for improving boot times on Bluey/Quenbi platforms.
BUG=b:478226455
TEST=Verified that 'clock_configure_qspi' can correctly look up and
set the 300MHz frequency in romstage.
Change-Id: I5320a68ff50a0d79daa2fc855b18b0f3ae819bbe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90886
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
With the current implementation of assert() for ENV_TEST, the printk()
function must be linked. As we are already using cmocka's mock_assert()
implementation for unit tests, those printk() calls within
assert-related macros should be changed to no-ops.
Also, disable __build_time_assert() for ENV_TEST.
Change-Id: Ia9bea29a32362d68dff89bb7bbf417126ac31fb7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90870
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs connected to the PCH-attached PCIe root port/m.2 socket need
a small delay in order to be reliably detected. Add a 15ms delay (the
default is 0) to ensure this.
TEST=build/boot Starfighter MTL 125H/285H with Samsung 970 EVO plus,
WD SN720, and Intel Optane P1600x SSDs in outer SSD socket. Ensure
all drives detected and bootable after both cold and warm resets.
Change-Id: I16ec0a313fc7cccb2807593c07db04cdbb59c979
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Properly advertise I/O ports decoded by H8 and PMH7. Therefore
implement read_resources() and set_resources() in coreboot and
advertise the ports using ACPI.
TEST=I/O ports are properly seen as fixed and assigned in
coreboot and the OS.
Change-Id: Iae1b72d2d565750020f2943804165b9d5d2efdfb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90723
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When APM_CNT_ACPI_DISABLE is issued during LPC init it will
enable SMI's when the EC asserts the GPE_EC_SCI GPIO, looking like:
[NOTE ] coreboot-25.12 x86_64 smm starting (log level: 6)...
[DEBUG] GPI (mask 0002)
This happens on all ec_read() calls whenever bits in the status
register change, causing lots of unnecessary SMIs at boot.
Cache the EC version string when it's first read and use the
cached version when writing SMBIOS tables.
While on it introduce defines for registers and drop function
from global scope.
TEST=Seen less SMIs during boot. Version string is still correctly
shown in dmidecode.
Change-Id: I514c628947c4e14f2379f7e2f265f28a9c7086d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This UPD is programmed for ADL, but not MTL and PTL. Add it to the
latter two so it functions as expected when set in devicetree for a
given PCIe root port.
TEST=build/boot Starlabs Starfighter MTL, verify Samsung NVMe drive
reliably detected in PCH-attached socket when timeout increased.
Change-Id: Iea744fed987d413c6487559005d668329a05fff4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Combine the size calculation and the CMDQ_SIZE_SEL bit setting into a
single write32 call for dsi->dsi_cmdq_size to optimize register access.
BUG=b:474187570
TEST=util/abuild/abuild -x -t GOOGLE_SKYWALKER -a --clean
BRANCH=skywalker
Change-Id: Idd08c8fab4120878c53fb94bf0e3cddb9a7eb513
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Also removes some dead code below which uses a dongle.py binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9b31a79f7637d31bbd824a8f6ad9137df429711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90818
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a default CBFS_SIZE for some boards to make sure they use
the whole BIOS region by default.
Change-Id: Ia032a9d5b3ba271390cc5f35ee734a1bbb1b90a4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The other AMD SoCs already use the XHCI_GEVENT define and since it's
defined as GEVENT_31, this won't change the behavior.
Change-Id: I895f453497f6e03e1aff237ba6d6ec1ebecfaaaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Correct a spelling error in the comment within the EC0 device block,
changing "reaading" to "reading".
Change-Id: I5cc57cad86f72be96e1465a1e8de9b9850adf7c1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
`tests/stubs/console.c` also implements printk for our test functions.
Change-Id: Ic6ad8832515b90f4706cb9c5b9d9525a25485992
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
A later patch changes the .config file which we use for our tests.
However that causes the PLATFORM_USES_FSP2_0 option to be enabled, which
in turn causes build errors in our tests, because the function is
obviously not defined in our tests. Create a stub function of sorts like
we do for other coreboot table entries.
It also moves the declaration of the `lb_string_platform_blob_version`
function to coreboot_tables.h, since it doesn't belong in the FSP header
file. Because of that we can also remove the
`if (CONFIG_PLATFORM_USES_FSP2_0)`
check, which makes the code a bit cleaner.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7721dfe4d287b2274a383bb7e5337b85a0f3f148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.
Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Moonstone hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=460038237
TEST=Build and boot to OS on Moonstone, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I8fd12d2f629977f939d11f26aef21552a947c5e3
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some Intel development boards have SuperIO located at address 4e instead
of "default" 2e.
In order to correctly initialize the SIO/EC, we need to allow access to
that address in bootblock.
For further information refer to #854345 (Intel CNDA).
TEST: Build/boot intel/pantherlake_crb (out-of-tree, pending clearance).
Make sure that RS232 is working and SIO ACPI tables are correct.
Change-Id: I7944a48738fe0146cdf94635a01153a5d2331b24
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90854
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch disables EC software sync specifically for the Microchip EC
on the ocelot board. This change selects
`GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC` for boards w/ microchip EC
(EC_GOOGLE_CHROMEEC_MEC) like ocelot.
This allows other ocelot variants (Nuvoton, ITE EC AIC) to potentially
enable EC software sync, which is not compatible with the Microchip EC.
TEST= Verified EC software sync functionality on a Nuvoton AIC ocelot
variant.
Change-Id: Ibcd6b0231a5390a9843419da86acee54811ec3d7
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89357
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Since Panther Lake, the FSP locks the TCC (Thermal Control Circuit) MSR
by default. However, Linux-based thermal management systems typically
configure this register from the operating system rather than the
firmware. Locking the TCC MSR in firmware prevents the OS from adjusting
thermal parameters as needed, potentially impacting system thermal
management and flexibility.
This commit explicitly sets the TccOffsetLock field to 0 in the FSP-M
configuration, ensuring that the TCC MSR remains unlocked after firmware
initialization.
BUG=b:474002582
TEST=MSR 0x1A2 is writable from the OS, as indicated by the successful
operation of
/sys/bus/pci/devices/0000:00:04/tcc_offset_degree_celsius on a
Fatcat device.
Change-Id: I445bc1408018d3de82919e46c8a368d93bbb1a77
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90718
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit exposes the TccOffsetLock UPD option in the FSP-M UPD
structure for Wildcat Lake platforms. Since Panther Lake, the FSP locks
the TCC (Thermal Control Circuit) MSR by default, which can interfere
with Linux-based thermal management systems that expect to configure
this register from the operating system.
By making TccOffsetLock available to coreboot, firmware integrators can
now prevent the FSP from locking the TCC MSR, thereby allowing the OS to
manage thermal parameters as needed.
BUG=b:474002582
Change-Id: I934dec88f88179c7859c6e1a35ea22c24bcfcbde
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90839
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SoCs may require additional programming to get the SPI TPM
work properly. This hook is especially needed if mainboard selects
TPM_MEASURED_BOOT_INIT_BOOTBLOCK and TPM is initialized before any
vendor silicon initialization code runs (FSP or OpenSIL).
Change-Id: I90dbcbfb554ac3cfbcf23d708c3440d27959c632
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
In our current tree this is always the case. The coreboot code (as far
as I know) doesn't have a hard requirement on that. But if these values
differ then it is usually always a mistake made by the programmer and it
is hard to catch since the value don't really depend on each other.
So until a time in which there comes a platform which needs a flashmap
that doesn't cover the whole flash, this check is introduced.
For that purpose we need to replace the default .config file for tests,
because otherwise the check won't match.
The config file that is used now is based on the fact that we use the
same mainboard for the `.config` as for the `fmap_config.h` in
`tests/include/tests/lib/fmap/fmap_config.h`
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8bc05a17a2630516ede949660b4fc428f199f3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90264
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update as per schematics.
Since the commit wasn't actually tested on the mainboard, keep the
BIOS region in the first 16M.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f1ae9d410804380d5465dcae35cc5965515506f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Update because the board by default has 16M flash.
TEST=build and run on the crater mainboard
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7ecb7721c523d8995e124b61715afac2090b3235
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Update as per schematics.
Since the commit wasn't actually tested on the mainboard, keep the BIOS
region in the first 16M.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6d3cdbec82539007c6a0923c1f1415882dd9f2c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Update it as per schematics.
Since the commit wasn't actually tested with the phoenix SOC, keep the
BIOS region in the first 16M.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6138d37be1b56178ce989996109157671f6973b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90265
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the SOC code based on the PPR for C1 stepping, doc 57238.
1. Turin CPU has less USB ports than Genoa, so the chip structure has
to reflect that. The number of ports has been reduced to match the
hardware capabilities.
2. Added early FCH initialization: legacy ISA devices, eSPI, I/O
decoding, UARTs, SMBus and SPI.
3. Updated AOAC device numbers.
4. Updated MMIO and I/O base addresses for CPU internal devices.
5. Added reserved RAM and MMIO reporting.
6. Adjusted root complex layout to match Turin IOHCs base addresses
and fabric IDs.
7. Extended chipset.cb devicetree to match the layout of devices on a
single socket Turin system.
Change-Id: I5272c1f2cd2aa259569d0bc6fa5c4073907b1673
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ESPI1 MMIO is reported in ACPI already, but the resource allocator
must also know about it to avoid the allocation of resources in that
range.
TEST=Boot Gigabyte MZ33-AR1 and verify that ESPI1 address (0xfec30000)
is reported for PCI device 00:00.14.3 in coreboot logs:
dev: PCI: 00:00:14.3, index: 0x3, base: 0xfec30000, size: 0x1000
Change-Id: Ic4024e6aa37bd7568dcecbd7cae29be9ae587a7f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
fwupd checks SMBIOS Type 0 BIOS Characteristics Extension Byte 2 bit 3
(UEFI Specification Supported) when deciding if UEFI capsule updates are
supported.
Set the flag when coreboot is built with the EDK2 payload.
Change-Id: I4d24deeca88cde5411225f8d113704f5a04e8a34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add support in mainboard to invoke LPASS Initialization.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG] BCM: Found address 0x00050048 for resource LP0
[INFO ] BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Change-Id: Icdcb8176639d4c6d24ab6cd2741d7e44e2370eb0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90852
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add API support to enable LPASS core clocks and vote for LP0 BCM
resource required for LPASS. This change includes support to enable
audio clocks.
LPASS is Low Power Audio Subsystem that runs audio and voice
processing on a dedicated DSP. This enables low-power audio operation
while the main CPUs remain in low-power states.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: If7684bee10d127866acac80e6aeefadaa177dc1f
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Let the user chose between 5500, 6400 and 7500MT/s.
Change-Id: I91171f252e83e409904031109ee084115f6b3708
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90825
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This somehow lost a few bytes when initially addded, so restore
the whole binary that was originally generated with spd_tools.
Change-Id: I7aa828c8e358a0d40597a265a8fc54e01ff105e8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90824
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MTE_TAG_ADDR macro is no longer used after the changes in CB:90144.
Remove the unused definition.
BUG=b:438666196
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a --clean
BRANCH=none
Change-Id: Ic71fa22292793162de882d3c764e7805301250c5
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The following error will be shown on non-NVMe SKUs.
[ERROR] DOMAIN: 00000000 missing read_resources
That's because when mainboard_needs_pcie_init() returns false, dev->ops
will be NULL, causing the '!curdev->ops || !curdev->ops->read_resources'
check to fail in device/device.c read_resources().
To prevent the misleading error message from showing up, for non-NVMe
SKUs, assign 'noop_domain_ops' to dev->ops.
BUG=none
TEST=emerge-tanjiro coreboot
BRANCH=rauru
Change-Id: If0f81aadda3fbde99f4df794cbdd885a607c9625
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90843
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a copy of genoa_poc OpenSIL directory with all genoa occurrences
changed to turin. Submodule has been omitted. Adjustment for Turin
OpenSIL will be made in subsequent patch.
Change-Id: I71e3b85f162971d6497783d4631a33780dc0e560
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90369
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds google_chromeec_set_lightbar_rgb() to allow mainboards
to manually control the individual LED colors. This is useful for
providing visual feedback during early boot or platform-specific
events, such as low-battery warnings.
TEST=Build and boot google/fatcat.
Change-Id: I146006511ea727787ea496b0674b67fa950ce8f2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update QUPV3_2_SE4 (ADSP I2C) configuration to use MIXED mode
instead of GSI. This allows the I2C controller for the charger
and fuel gauge to handle both GSI (DMA) and non-GSI transfers,
ensuring better compatibility during different boot stages.
BUG=b:472358270
BRANCH=None
TEST=TBD.
Change-Id: Ie2ed3cd6991c3d98b7902c1331e68ec5a4f35d92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
