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vc/amd/fsp: Add SMBIOS Type 19 and 20

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TEST=Boot glinda based mainboard and see Type 19 and 20 entries using
     dmidecode tool.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9a0abab9a5324f83659180a3842a8b5d9c6b3820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Maximilian Brune 2025-04-16 20:58:00 +02:00 • committed by Matt DeVillier
commit 81af46e68b
7 changed files with 64 additions and 1 deletions
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2
src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
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@ -10,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 2 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 8 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 1 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_SUPPORT 1

52
src/vendorcode/amd/fsp/common/dmi_info.h
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@ -185,8 +185,60 @@ typedef struct {
#endif
} __packed TYPE17_DMI_INFO;
/// DMI Type 19 - Memory Array Mapped Address
typedef struct {
OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
///< of a range of memory mapped to the
///< specified physical memory array.
OUT UINT32 EndingAddr; ///< The physical ending address of the
///< last kilobyte of a range of addresses
///< mapped to the specified physical memory array.
OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
///< with the physical memory array to which this
///< address range is mapped.
OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
///< form a single row of memory for the address
///< partition defined by this structure.
OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
///< memory mapped to the specified Physical Memory Array.
OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
///< memory mapped to the specified Physical Memory Array.
} __packed TYPE19_DMI_INFO;
///DMI Type 20 - Memory Device Mapped Address
typedef struct {
OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
///< of memory mapped to the referenced Memory Device.
OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
///< the Memory Device structure to which this address
///< range is mapped.
OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
///< the Memory Device structure to which this address
///< range is mapped.
OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
///< with the Memory Array Mapped Address structure to
///< which this device address range is mapped.
OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
///< Device in a row of the address partition.
OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
///< an interleave.
OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
///< referenced Memory Device that are accessed in a
///< single interleaved transfer.
OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
///< memory mapped to the referenced Memory Device.
OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
///< a range of addresses mapped to the referenced Memory Device.
} __packed TYPE20_DMI_INFO;
/// Collection of pointers to the DMI records
typedef struct {
OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
OUT TYPE17_DMI_INFO T17[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL]; ///< Type 17 struc
#ifdef AGESA_STRUCT_T19_REGION_SUPPORTED
OUT TYPE19_DMI_INFO T19[AGESA_STRUCT_T19_REGION_SUPPORTED];
#endif
#ifdef AGESA_STRUCT_T20_REGION_SUPPORTED
OUT TYPE20_DMI_INFO T20[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL][AGESA_STRUCT_T20_REGION_SUPPORTED]; ///< Type 20 struc
#endif
} DMI_INFO;

3
src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
View file

@ -2,7 +2,6 @@
/*
* These definitions are used to describe memory modules physical layout
* TODO: Update for Glinda
*/
#ifndef SOC_DMI_INFO_H
@ -11,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 16 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 3 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 31
#define SMBIOS_3_2_SUPPORT 1

2
src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
View file

@ -10,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 12 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 1 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_SUPPORT 1

2
src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
View file

@ -10,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 12 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 1 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_SUPPORT 1

2
src/vendorcode/amd/fsp/picasso/soc_dmi_info.h
View file

@ -10,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 1 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 4 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 1 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#endif /* SOC_DMI_INFO_H */

2
src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
View file

@ -10,6 +10,8 @@
#define AGESA_STRUCT_SOCKET_COUNT 2 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 8 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count
#define AGESA_STRUCT_T20_REGION_SUPPORTED 1 ///< Max SMBIOS T20 Memory Region count
#define AGESA_STRUCT_PART_NUMBER_SIZE 21 //TODO check
#define SMBIOS_3_2_SUPPORT 1