Update the SOC code based on the PPR for C1 stepping, doc 57238.
1. Turin CPU has less USB ports than Genoa, so the chip structure has
to reflect that. The number of ports has been reduced to match the
hardware capabilities.
2. Added early FCH initialization: legacy ISA devices, eSPI, I/O
decoding, UARTs, SMBus and SPI.
3. Updated AOAC device numbers.
4. Updated MMIO and I/O base addresses for CPU internal devices.
5. Added reserved RAM and MMIO reporting.
6. Adjusted root complex layout to match Turin IOHCs base addresses
and fabric IDs.
7. Extended chipset.cb devicetree to match the layout of devices on a
single socket Turin system.
Change-Id: I5272c1f2cd2aa259569d0bc6fa5c4073907b1673
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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