Adds the abillity to use a custom u-boot repo and a custom branch.
Change-Id: I15df8a41d3d94ca0559abc964792035651b3d8b2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89616
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently no one ever build this using UBOOT_MASTER, because it is
missing the "cd $(project_dir)" before git fetch.
I have also no idea what the git show was originally supposed to do.
So just remove them both and move on.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2f26660131ce91420a951fb33ac0eef89371745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89615
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add a new function google_chromeec_has_kbbacklight() to check if the EC
has keyboard backlight capability. The function first tries the EC
feature flag (EC_FEATURE_PWM_KEYB), falling back to a read test if
unavailable. The EC command ec_cmd_pwm_get_keyboard_backlight() returns
-1 if the device does not have a keyboard backlight.
This function will be used in subsequent commits to guard setting the
keyboard backlight at boot and the visiblity of a CFR option setting.
TEST=tested hooked up to a CFR option to set the keyboard backlight
at boot, with visibility controlled by backlight presence, on a
range of Chromebooks with and without keyboard backlight support.
Change-Id: I74daf7a63f06239d2ba3915221555af494a9340f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89827
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`ToString(byte x)` is undefined behavior per the ACPI spec, which
causes Windows to discard the battery device status entirely.
Fix this and improve performance of the BRSX method by using an array
to store the characters read, calling ToString() only once at the end.
TEST=build/boot Win11 and Linux on google/rex, verify battery status
reported properly under both OSes.
Change-Id: I4e5aea3b2763a3c4433abe95c3a41d218fcd06c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set the GPE0 registers (DW0, DW1, and DW2) to configure General
Purpose Events (GPEs) for the Lapis variant. This configures
GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups.
This patch ensures the variant can override the default baseboard
(fatcat) GPE settings, which may not align with the variant's
(aka lapis) hardware.
BUG=b:414614106
TEST=Able to override PMC GPEs as per google/lapis configuration.
Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Configure the Touch Host Controller (THC) devices 0 and 1 on the
Fatcat/Lapis variant to use HID over I2C mode.
This change explicitly sets the thc_mode[0] and thc_mode[1] registers
to THC_HID_I2C_MODE in overridetree.cb. This is necessary to correctly
initialize the THC for devices like touchpads or touchscreens that
communicate using this protocol.
BUG=b:455442712
TEST=Able to build and boot google/lapis with functional touchpad.
Change-Id: I7c9a62afab396cb38775eaa5e96f2dc7ed773216
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89818
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Touch Host Controller (THC) requires its dedicated VGPIO pins to
remain enabled as a General Purpose Event (GPE) source for the system
to wake up on touch events.
This change introduces override_tier_1_gpio_chip_config to explicitly
check the thc_wake_on_touch status for each enabled THC interface.
If any wake-on-touch functionality is active, the Tier-1 GPE
configuration (pmc_gpe0_dw0) is overridden to ensure the GPP_VGPIO
bank is included.
This guarantees that the VGPIO pins dedicated to THC are always
monitored as a wake source when required by the platform
configuration.
BUG=b:414614106
TEST=Able to build and boot google/fatcat.
Change-Id: Ia1165c167850f5d66a8c5a85e3ec64f80e7a40da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89817
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add stop pin control for G2 touchscreen.
BUG=b:456578327
TEST=build and verified Touchscreen work normally.
Change-Id: I0581fffdc2ec16a1c36b2e716b0fae27bad465ee
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89813
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.
Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.
The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4
This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.
TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed
Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is a more suitable place for these definitions as
it contains all other ECRAM offsets.
Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89695
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the Moonstone Schematic Proto 2.0 design, disable
Thunderbolt support for TCSS_PORT0 on the MB and TCSS_PORT1
on the DB.
Schematic: Kinmen(ZDQ)_Proto2.0_Moonstone_1014.pdf
BUG＝none
TEST=emerge-fatcat coreboot
Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89819
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The left-up and right-up orientations were swapped. Fix it to align
with boot logo and depthcharge screen.
BUG=b:406725440
TEST=Verify all 4 panel orientation on Google/Felino.
Change-Id: Ib0d08d4b2aa697129d854c15e081c7765e542060
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure FMAP_CBFS_BASE is aligned to 4k (0x1000) to match typical flash
sector boundaries. This allows flashrom to read/write only the COREBOOT
region using the --fmap layout option without extending the boundaries.
Previously, the COREBOOT region would start immediately after the FMAP
region (at FMAP_BASE + 0x200), which is not sector-aligned. Most flash
chips support a minimum 4k sector size, so flashrom would automatically
extend the region boundaries and emit a warning.
This eliminates warnings from flashrom such as:
Region [0x00c54000 - 0x00c541ff] is not sector aligned!
Extending end boundaries by 0x00000e00 bytes,
from 0x00c541ff -> 0x00c54fff
TEST=build/boot google/gladios, update using --fmap and verify no
warnings regarding region alignment.
Change-Id: Ie4963bbef546aa23364bb9c1c347c5eb5bfeaf8e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The generated build/fmap.fmd file was displaying region sizes and
offsets in a mix of decimal and hexadecimal formats, making it harder
to read and compare values. This change ensures all numeric values are
consistently printed in hexadecimal.
The conversion to hex is done in two places:
1. For conditional FMAP entries (MRC_CACHE, SMMSTORE, SPD_CACHE, VPD,
HSPHY_FW, CONSOLE), the _tohex conversion is applied at entry
definition time. This is necessary because these entries may be
empty when their respective CONFIG options are disabled, and the
conditional logic happens before the sed substitution.
2. For unconditional values (ROM_SIZE, BIOS_BASE, BIOS_SIZE,
FMAP_BASE, CBFS_BASE, CBFS_SIZE), the _tohex conversion is applied
directly in the sed command when generating fmap.fmd. This keeps
the base variables in decimal form for continued use in arithmetic
operations.
All internal calculations continue to use decimal values. Only the
final output strings that are written to fmap.fmd are converted to hex
format.
Before:
SI_BIOS@29032448 4521984 {
SMMSTORE@65536 0x40000
RW_SPD_CACHE@327680 4096
After:
SI_BIOS@0x1bb0000 0x450000 {
SMMSTORE@0x10000 0x40000
RW_SPD_CACHE@0x50000 0x1000
Change-Id: I48cc39b430943cb4923955b5e3d64ad6dd24a6cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89836
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Enable rp5 if the FW_CONFIG bits for WIFI are set to WIFI_PCIE_6 or
WIFI_PCIE_7.
BUG=b:444509417
TEST=emerge-ocelot coreboot chromeos-bootimage', flash ocelot and
verify CNVI and PCIe WiFi solutions are detected correctly.
Change-Id: I077bfc48a82c354d1011ef756aa6aa55bf6951cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The `EC_STARLABS_ADD_ITE_BIN` Kconfig option is only meaningful on
Star Labs boards with an ITE EC, i.e. those with `EC_STARLABS_ITE`
selected. So, add a "depends on" line so that the former option is
only visible on applicable boards.
TEST=`EC_STARLABS_ADD_ITE_BIN` no longer shows up for qemu-q35.
Change-Id: Ifb40d8b432d2abeadba2a970010dac126e4b7418
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
PCIe Root Port 5 uses both CLKSRC 1 and CLKSRC 2, but coreboot's
devicetree only allows configuring a single clock source per port. Add
a comment to document that CLKSRC 2 is implicitly used by the hardware.
Change-Id: I9b54d97fa5e4e4e80a58392a7592bab91e00824d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Expose the PchHdaMicPrivacyMode UPD parameter in the FSP-S
configuration structure for WildcatLake. This parameter controls
the HD Audio microphone privacy mode, allowing mainboards to
configure whether microphone privacy is hardware-managed,
firmware-managed, forced to mute, or disabled entirely.
TEST=Built WCL FSP successfully with this change.
Change-Id: If48c684aea09291715718a6e8fb400b9550aab61
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.
BUG=none
TEST=Boot to OS on fatcat device and check performance.
Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to using `objdump -f`, which consistently prints the line
"file format <format>" across modern binutils versions, and extract
the architecture format from that output. This restores correct
toolchain detection on Ubuntu 25.10 and other systems with binutils
≥ 2.43, without breakng older versions.
Before:
DEBUG: obj_type:
/tmp/temp.rrDQ8i.o: file format elf64-x86-64
DEBUG: obj_arch:
After:
DEBUG: obj_type:
/tmp/temp.8GsK08.o: file format elf64-x86-64
architecture: i386:x86-64, flags 0x00000000:
start address 0x0000000000000000
DEBUG: obj_arch: elf64-x86-64
Change-Id: Ic09304f9e81580bbe1c0bb4910c0cc534d3d2816
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89643
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 8a2c04e04d.
Reason for revert: The hang is still present
Change-Id: Iba3c2b684cce3adefecd175d0ef09a5d051410ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89805
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 80861a9f69 ("mb/starlabs/starlite_adl: Add CFR option for
USB card reader") added support for the USB card reader, but did
not add the corresponding ACPI entries.
Change-Id: Ibef1b8412d5f51ffbfa715bb1ee80f73411dd3b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89772
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the most commonly shared Nuvoton SIO logical device numbers into
one central header. It will be handy when they start sharing per-LDN
setup code.
Block iasl from seeing anything other than the LDNs.
Rename the re-inclusion guard symbol as its use is no longer limited to
pre-RAM stages.
It references NCT677x because that reference is hidden in every single
Nuvoton SIO chip datasheet in my possession.
Change-Id: Ibf01c0e0ffdecbedc34df62b582e3be0c5c0a852
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently wwan_power.asl clears gpio WWAN (PERST) during power-off.
Caboc project uses a MOS reverse pin to connect GPP_A21
(WWAN_ASPM_EXIT) to WWAN (PERST). Based on this design, uses STXS to
keep GPP_A21 high to meet power-off sequence.
Set T1_OFF_MS to 20ms and T2_OFF_MS to 10ms as HW engineer requested.
BUG=b:453512678
TEST=emerge-brox coreboot
HW enginer has measured and confirms WWAN power-off sequence.
Change-Id: I202a370dba2ba1dec61b1ad44140674bd470ba6e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The documentation has been adjusted to include additional variants,
and brushed up a bit for clarity.
Change-Id: Ia7711d5105e568113de219b1aa43e3a5d50aaf9c
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Call the `report_memory_config()` and `setup_sdram_meminfo()` functions,
which were factored out into shared raminit code in previous patches. As
the SPD data is not readily available where `setup_sdram_meminfo()` gets
called, add a function to get it from the saved data, as it is available
in a global context. Technically speaking, the "mighty ctrl" variable is
also static (thus global), but it is only meant to be used within native
raminit code and is only static to avoid nuking the stack (it is huge).
Change-Id: Ia2c0946f55748e38bb5ccb5cb06721aeb77527e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89600
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `report_memory_config()` function to shared raminit code, both
to deduplicate the code and to allow native raminit to make use of it.
Change-Id: I8b3c695c0a266634a42b0303e4f1ea699301c26b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89599
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `setup_sdram_meminfo()` function to shared raminit code
to deduplicate it as well as to allow native raminit to make use
of it, which will be done in a follow-up.
When consolidating the functions, the only functional difference
is that the Broadwell MRC.bin path reports memory frequencies in
MHz whereas the Haswell MRC.bin path reports them in MT/s. Since
this data is used to populate SMBIOS tables, which expect memory
frequencies in MT/s, using MT/s is the right choice.
Given that SPD data is handled differently in the three RAM init
implementations (Haswell MRC, Broadwell MRC, native raminit), we
have to abstract the SPD data pointers a bit. This is done using
an array of pointers.
While we're at it, add some TODO comments to note limitations of
the code. The idea is to fix those in follow-up commits.
Change-Id: I1f81bf18a9e856d80f8e4d7bda65089e999957f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reconfigure I2C controller settings to disable I2C1 and enable I2C6
for the mc_rpl1 mainboard. This change reflects the updated hardware
configuration requirements.
Changes:
- Disable I2C controller 1
- Enable I2C controller 6
TEST=Build and boot tested on mc_rpl1 mainboard.
Verified I2C6 functionality and confirmed I2C1 is disabled with
`lspci -v | grep -A 5 "Serial bus controller"`. The output
confirms that I2C6 (PCI 00:10.0) is enabled and I2C1 (PCI 00:15.1)
is disabled because it is absent.
```
00:10.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #2 (rev 01)
Subsystem: Intel Corporation Alder Lake-P Serial IO I2C Controller
Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 4
Memory at 80a12000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [80] Power Management version 3
Capabilities: [90] Vendor Specific Information: Len=14 <?>
```
Change-Id: I4867062743ee10b34f94a1e588a10115b553a16e
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Test=Change fan mode on byte_adl in edk2 and verify correct value
is written to the EC memory using `ectool -d`
Change-Id: I93d4be663a059abb973ad6abf2e60d40f56ed6c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Pujjoga and pujjogatwin projects are both going to be single RAM device, so add single ram configuration.
Schematic version: 500E_GEN4S_ADL_N_MB_250920
Below log show the device can recognize the single dram.
[INFO ] SPD: module type is LPDDR5X
[INFO ] SPD: module part number is H9JCNNNBK3MLYR-N6E
[INFO ] SPD: banks 8, ranks 1, rows 16, columns 11, density 16384 Mb
[INFO ] SPD: device width 16 bits, bus width 16 bits
[INFO ] SPD: module size is 2048 MB (per channel)
[INFO ] Device only supports one DIMM. Disable all other memory
channels except first two on each memory controller.
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x76fff000 254 entries.
[DEBUG] IMD: root @ 0x76ffec00 62 entries.
BUG=b:445629015
BRANCH=none
TEST=Build and boot to OS. Verify functions work.
Change-Id: I22e8335432e6e65bd1640bf6a6dec03691e3462e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89221
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure MMU for framebuffer region only when framebuffer region
exists (i.e., REGION_SIZE(framebuffer) > 0). Otherwise, the MMU would
raise assertion.
[INFO ] Mapping address range [0x0000040000000:0x0000240000000) as cacheable | read-write | non-secure | normal
[INFO ] Mapping address range [0x0000040000000:0x0000040100000) as non-cacheable | read-write | non-secure | normal
[DEBUG] Backing address range [0x0000040000000:0x0000080000000) with new L2 table @0x020da000
[DEBUG] Backing address range [0x0000040000000:0x0000040200000) with new L3 table @0x020db000
[INFO ] Mapping address range [0x0000000000000:0x0000000000000) as non-cacheable | read-write | non-secure | normal
[EMERG] ASSERTION ERROR: file 'src/arch/arm64/armv8/mmu.c', line 194
BUG=b:454457496
TEST=The assertion does not occur.
Change-Id: I8ab17bd289cd41a4568fddff2e556e5e49b1e6a4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Increase the ME region by 4KiB to match the IFD that is used for
both the Alder Lake and Twin Lake versions.
Change-Id: I22fa2388ed5660b959815be00029c07cac2b5244
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89761
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch corrects the EC sync IRQ configuration logic to properly
handle different ocelot board variants:
1. Update conditional compilation in ec.h to exclude OCELOTMCHP and
OCELOTMCHP4ES variants from EC_ENABLE_SYNC_IRQ, as these boards do
not have the EC sync IRQ connected.
2. Restructure GPIO definitions in gpio.h to:
- Set EC_SYNC_IRQ to 0 (not connected) for OCELOTMCHP, OCELOTMCHP4ES,
variants.
- Enable EC_SYNC_IRQ on GPP_E08_IRQ for OCELOT, OCELOT4ES, OCELOTITE,
and OCELOTITE4ES variants.
3. Configure GPP_E08 pad appropriately in gpio.c:
- Set as NC (not connected) for OCELOTMCHP variants.
- Configure as APIC interrupt for other variants that support EC sync
IRQ functionality.
BUG=NONE
TEST=Build and boot on Ocelot variants.
Change-Id: I96e92ed9d6fa5b586ab9c0faf73d08b55abe4795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89459
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from
350ms to 330ms. Validation on Prade shows the controller initializes
reliably within the reduced timing. It will be able to complete the
following steps before vccs on.
1. TP Reset
2. Get HID Description
3. HID Reset/HID Power On
4. Get Report Descriptor/Get Feature Report
Verification results are in b/455053468 comment#3
BUG=b:455053468
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence
Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.
Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add config `MEDIATEK_DSI_CPHY` to enable the MIPI C-PHY interface on
mt8189, including necessary register definitions and integrating with
the common MIPI driver, dsi_register_v2.
BUG=b:433422905,b:428854543
TEST=Check display initialization log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iac6c1b6d47331b63e7b45157bd60da93f104b0ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89620
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data
rate calculations, timing configurations, and register settings for
C-PHY operation.
To improve code reusability, the D-PHY and C-PHY specific
implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`,
respectively.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
(cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add a new member 'flags' to the panel structure in panel.h, and define
`PANEL_FLAG_CPHY` to indicate C-PHY interface support. This change
enables panel drivers to check and handle C-PHY panels.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=build passed
Signed-off-by: Bincai Liu bincai.liu@mediatek.corp-partner.google.com
Signed-off-by: Vince Liu vince-wl.liu@mediatek.corp-partner.google.com
Change-Id: I4c35ad2cb6fc2289598ae47b3abf1c6c706dad42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
