Select GBB_FLAG_ENABLE_ADB in Kconfig for the Bluey board. This is
required to support ADB debugging during the current development
phase.
Note: This is intended as a temporary measure (FIXME) and should
likely be reverted before production.
Change-Id: I9c8c2a315fcf91e4b51d25ee4e00490db7e33486
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces a new Kconfig option,
`CONFIG_GBB_FLAG_ENABLE_ADB`, to allow enabling ADB.
This option, when enabled, sets the corresponding GBB flag (0x80000000).
This flag can then be utilized by the operating system to enable the
ADB.
TEST=Able to connect the google/quenbih from host device using ADB cable.
Change-Id: I680c1f47045255a5ed49b0bb6c6fb94bc054c278
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove WCL_ID_2 through WCL_ID_5 entries from the power mapping table
supports a single SKU configuration.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots
Change-Id: I95a8069c9b637c35936e6c0e5de257f7acbd8463
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91448
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the minimal NVMe admin queue and Security Send/Receive helper code
used by the SMM resume unlock path.
TEST=tested with rest of patch train
Change-Id: Iaf4a9e23d399a093139edffc724f2b2661ca3bb1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add the Intel TCG storage encoder subset used by the OPAL S3 unlock
path. Compiled only when TCG_OPAL_S3_UNLOCK is enabled.
TEST=tested with rest of patch train
Change-Id: Iecbe2011761e913b73541192ccb3a9e9cff6a87c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91044
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a generic configuration option for SMM-assisted TCG OPAL NVMe
unlock on S3 resume.
This also defines the APMC command IDs and the payload->SMM ABI
structure used to pass the OPAL password into SMM.
TEST=tested with rest of patch train
Change-Id: Id99ace7c17a311b65519023be4118c5b20ddecf9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91043
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate RAM ID for BWMYAX32P8A-32G
DRAM Part Name ID to assign
BWMYAX32P8A-32G 4 (0100)
BUG=b:493358217
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia43dc45874e57c92c5b377c5afd073ef9ced7c57
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91686
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yanqiong Huang <huangyanqiong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since moxoe is a box product using DDR5 SODIMM, remove SAGV enable to
use the default disabled state for better memory stability.
BUG=b:481186489
TEST=Build and boot, verify SaGv is disabled via FSP logs.
Change-Id: I1e07f7cb32b7387a7b96c9666eb809983559f7f4
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since kulnex is a box product using DDR5 SODIMM, remove SAGV enable to
use the default disabled state for better memory stability.
BUG=b:480035819
TEST=Build and boot, verify SaGv is disabled via FSP logs.
Change-Id: I37d56a33a1ba48ef105e03ca1a24c11291646fc0
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In CPHY mode, mtk_dsi_cphy_vdo_timing previously packed multiple values
into hfp_byte:
- Bits [7:0]: actual HFP byte count
- Bits [30:16]: hs_vb_ps_wc
- Bit 31: HFP_HS_EN flag
The previous error check treated the entire compound value as the HFP
byte count, resulting in false error messages like:
"Calculated hfp_byte -1850408952 and hbp_byte 4 are too small"
This patch refactors mtk_dsi_cphy_vdo_timing to return hfp_byte and
the upper bits (hfp_wc_upper) separately:
- hfp_byte now consistently represents the actual HFP byte count for
both CPHY and DPHY modes
- hfp_wc_upper contains hs_vb_ps_wc and HFP_HS_EN for CPHY (0 for DPHY)
- The values are combined when writing to dsi_hfp_wc register
This approach:
- Eliminates the need for mask operations in the caller
- Simplifies hfp/hbp validation and adjustment logic
- Makes hfp_byte semantically consistent across CPHY/DPHY
BUG=b:489932059
TEST=Boot and verify display output on MT8189 CPHY panel
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
Change-Id: I46229c35f978a88276f4ae2a4582b2ea4164c1db
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91683
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Downstream bridges share the same PCI device ID as the upstream
bridge but have no firmware mailbox. Sending commands to them
causes timeouts. Add a forward declaration of dtbt_device_ops
to detect and skip bridges whose parent is also a dTBT device.
Tested on thinkpad t480: The 5s timeout is now gone.
Change-Id: I96febb0e52e0ffbe52a237212b8f708a7b05c6d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ADL programs this but MTL and PTL do not, so add it to the latter two
for consistency.
Change-Id: I8c982fcc810b3783cba4c66754df2b555bce6dfc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90878
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The PCIE_RP_BUILT_IN flag test is used only as a boolean condition, so
the double-negation is unnecessary. Also fix the comment grammar.
Change-Id: I5e1ff5848d9cedb2385892c795297719ccc1d5cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Switch Intel common block smihandler to use the generic x86
smm_save_state_ops instead of its own custom struct. Replace
find_save_state() and get_io_misc_info with apmc_node; use
node-based get_reg/set_reg functions. Alias em64t100_ops and
em64t101_ops for cpu/x86 save_state.c consumers.
TEST=tested with rest of patch train
Change-Id: Ie64478ccfdc0a0bda4354641aba06705e2c8c70d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reserve a small persistent SMRAM subregion for OPAL S3 unlock state, so
the payload-provided OPAL secret can survive SMM handler reload on S3
resume.
Expose the region base/size to SMM via smm_runtime and provide an
accessor for SMM code. Clear the region on cold boot/reboot, but
preserve it when waking from S3.
TEST=tested with rest of patch train
Change-Id: Ib1e92edb31c845367afe6185e5fa18ab1bc71108
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove __weak to ensure variant-specific memory functions properly
override the default implementations in the baseboard.
BUG=b:491711748
BRANCH=firmware-brya-14505.B
TEST=Build and boot on kulnex, verify memory initialization.
Change-Id: I61e33a215d41d25cc1f64866e653c0f1d4eb8ba8
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91693
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reference code version 1.9.1 sets `SAPMCTL` bit 0 just before setting
`BIOS_RESET_CPL` bits 0 and 1. Do the same thing in coreboot.
Change-Id: I36e24d2a3bd754e56df59a1e996d285ec6bf5205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91632
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Intel Document 492662 (Haswell System Agent BIOS Spec), Rev 1.6.0 states
that `ARCHDIS` (VT engine BAR, offset 0xff0) has to be written fully, as
well as several other things that were not done properly in coreboot. As
these steps are Haswell-specific, introduce two helper functions to test
if the CPU is Haswell or Broadwell.
Intel Document 535094 (Broadwell BIOS Spec), Rev 2.2.0 contains the same
steps for Broadwell. To permit unifying Haswell and Broadwell, implement
the Broadwell steps as well.
Change-Id: I077e064754720d9f9f627733c954712a2b24b5b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91631
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Instead of open-coding function-to-DEVEN-bit mapping thrice (using
a different implementation each time), introduce `deven_for_peg()`
to map the PCI function number to the corresponding DEVEN bit. Use
the PCI function number as primary parameter, instead of passing a
`pci_devfn_t` around and getting the PCI function number from that
using two macros.
Change-Id: Ia2f7cdcff3c95f831269fa51f9bfc60bef0907a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91630
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These can and will be used in other files in subsequent commits.
Change-Id: Iba0515151252b22f0211e8ab1470c70dfd172929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This function prints CPU information, so it makes sense for it to be
part of CPU code. The version in CPU code prints a bit more info but
is otherwise equivalent. After all, this is just logging some info.
Change-Id: I2a9d8a42f78efab6206710fada1d64fa79e8056e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91627
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Abdelkader Boudih <coreboot@seuros.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the entries for Crystalwell and Broadwell ULT, and add the CPUIDs
for Crystalwell B0 and Broadwell G0. Also drop a now-done FIXME comment.
Change-Id: Ib5293b5a0ef3321678c68363fb4bc8999b10cd01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91626
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 8b0636e06f ("cpu/intel/haswell: Clean up CPUID definitions")
used the wrong value for the `CRYSTALWELL_FAMILY` macro. Also, as per
Intel document 634961-024 (Broadwell-H Specification Update), the one
production Broadwell Trad stepping is G0, not C0. And for the sake of
completeness, add the `BROADWELL_FAMILY_TRAD` macro.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I25be5289997000e116cc36cf427a9d4970a3ec1b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91625
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This function prints CPU information, so it makes sense for it to be
part of CPU code. Subsequent commits will update the CPUID table and
make the Haswell northbridge code also use it.
For now, rename the static function in `nb/intel/haswell` to avoid a
name clash. It will be dropped in a follow-up anyway.
Change-Id: I6b26fddd4e899b692f4122921db1c70f4b16b4f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91624
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The register at MCHBAR offset 0x5418 is named `INTRDIRCTL` on Haswell,
as well as earlier platforms. Sync the Haswell and Broadwell codebases
by renaming `MCH_PAIR` to `INTRDIRCTL` on Broadwell.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I0b37927ebec634b6e48623f75789723cf518c3ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Yes, the "Coding Style" page of the coreboot docs states the following:
Bulk style changes to existing code ("cleanup patches") should
avoid changing existing style choices unless they actually
violate this style guide, or there is broad consensus that the
new version is an improvement. By default the style choices of
the original author should be honored.
However, when attempting to unify two codebases (Haswell and Broadwell),
style differences only make it harder to find the functional differences
between the codebases. So, it makes sense to unify the code style first,
so that only functional differences remain. Especially if these cosmetic
alignment changes are reproducible, i.e. they don't change the resulting
coreboot.rom when using `make BUILD_TIMELESS=1` to build.
Sort includes alphabetically, unbreak some long lines that are less than
96 characters long, combine variable declaration and initialisation, use
C-style comments, use one line for printk strings (easier to use grep to
find them this way), constify some values the compiler already knew they
were constant (they get inlined anyway), remove unnecessary parentheses,
fix space usage around operators, align some comments with Haswell code,
rename a few things for consistency with Haswell, use an early return in
place of an if-block (like Haswell does), drop a few unused includes and
include `types.h` from files that need it.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I872068e93f1960d90a914193ccb346fc77652220
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91620
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This pulls in the following changes from the submodule:
- README.md: Add psirt email address
- MDN: Update ABL to version 3516B01Bh
- MDN: Upgrade microcode patch to 08A0000Bh
- cezanne: Update ABL to 0x23216072
- cezanne: Upgrade microcode patch to 0A500014h
- Upgrade microcode patch of PCO to 0810810Eh, Pollock to 08200105
- Picasso/Pollock/Dali: Update SMU Fimemware
- Update Phoenix FP7/FP8 binaries to PI release 1.2.0.0d
- Add Phoenix AM5 binaries from PI release 1.2.7.0
- MDN: Update mendocino SMU to 90.49.0
- MDN: Upgrade microcode patch to 08A0000Ch
- MDN: Upgrade ABL to 3516B021
- CZN: Updata PSP stage 2 to E5.11.11.75
- PCO: Upgrade ABL to CABLRV26012800
- add binaries for Strix, Krackan, and Krackan2e
- MDN: Update PSP to v00.3C.04.18
- CZN: Upgrade ABL to RABLCZN23216073
- FWDEV-177733: Upgrade PSP version to 75.11.11.20
- move the Phoenix AM5 files to a location more in line with the rest
- add binaries for Strix Halo
Change-Id: I7404a53b0c3b27d73d6e0633520e6040539e992f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate a signed UEFI capsule from the final coreboot ROM image using
EDK2 BaseTools.
When using an EDK2 payload and enabling DRIVERS_EFI_UPDATE_CAPSULES and
DRIVERS_EFI_GENERATE_CAPSULE, the build produces build/coreboot.cap once
the ROM is finalised (after all files were added to CBFS). The capsule
can also be generated explicitly with `make capsule`.
Move the capsule generation and certificate preparation into
payloads/external/edk2/Makefile, including generating the trusted root
certificate PCD include via BinToPcd.
Support capsule flows with an embedded FmpDxe driver by optionally
embedding FmpDxe.efi into generated capsules, and wiring the
embedded-driver Kconfig options through to the EDK2 payload build and
capsule generation.
Always set PersistAcrossReset on the capsule. Make InitiateReset
configurable (default off) because Linux rejects capsules with
InitiateReset when writing via /dev/efi_capsule_loader.
Use CONFIG_DRIVERS_EFI_MAIN_FW_VERSION for GenerateCapsule
--fw-version, but fall back to parsing a leading <major>.<minor> from
CONFIG_LOCALVERSION when it is left at 0. If
CONFIG_DRIVERS_EFI_MAIN_FW_LSV is 0, use the resolved firmware version.
Document capsule generation and embedded driver configuration.
Corresponding edk2 patches can be found at:
https://github.com/tianocore/edk2/pull/12053
Change-Id: I5f56b894d40ddb49f3158bb72f0143d0ebe9c34c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90862
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QEMU sbsa-ref machine has a GICv3 ITS at 0x44081000 that handles
MSI/MSI-X translation for PCI devices. Without describing the ITS in
ACPI tables, Linux cannot set up MSI interrupts, causing warnings like:
WARNING: CPU: 1 PID: 1 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x40/0x58
xhci_hcd 0000:00:04.0: xHCI Host Controller
Add GIC ITS base address to the address map and implement
platform_get_gic_its() so the common MADT generation code emits
a GIC ITS entry.
Select ACPI_IORT and implement acpi_soc_fill_iort() to generate an
IORT table with an ITS Group node and a Root Complex node that maps
all PCI RIDs 1:1 to ITS device IDs.
Tested with Fedora 41 and a qemu-xhci USB controller.
Change-Id: I9366968aac855dae808f6f0c73f1d3ec644bbeff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91668
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QEMU sbsa-ref machine maps PCI I/O port space at 0x7fff0000.
Set io_port_mmio_base so that PCI I/O port accesses are correctly
translated to MMIO on aarch64.
This is needed for PCI device drivers that may use I/O port BARs,
such as the QEMU bochs display driver which already compiles and
links for this target via the existing DRIVERS_EMULATION_QEMU_BOCHS
Kconfig.
Change-Id: I6a06c4c3a48c5d3409009f10b089a3537ccec8a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The current implementation only supports sink mode on the debug access
port, which is used for charging. To enhance debugging capabilities,
expand the support to include source mode.
Refactor the Kconfig option to HAVE_DEBUG_ACCESS_PORT_SOURCE_SINK and
update the initialization logic to configure both SRC and SNK modes
via the PMIC's SCHG_TYPE_C_DEBUG_ACCESS registers. This allows the
debug port to serve as a power source or sink as required by the
attached debug hardware.
BUG=none
TEST=Verify debug port modes on Google/Quartz.
Change-Id: I3ec45d9cdc0ec6e723d10792f4e347462cecd2ed
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91670
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The ADSP GSI initialization/loading is needed in both
normal boot and the off-mode/low-battery charging path. This patch
moves it before the conditional mainboard initialization skip, so it
runs in all cases.
TEST=Able to build and boot google/bluey.
Change-Id: I6237154f8701d5f7f9e1e0b20378cb8e8be39fca
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
dsi-phy1 and dsi-phy2 are currently controlled using hardware voting,
however there is a low probability of power-off failure during the boot
process. Since dsi-phy1 and dsi-phy2 are not shared with different XPUs,
there is no need to control them using hardware voting. Change the
control method of dsi-phy1 and dsi-phy2 from hardware voting to software
control to fix the power-off failure issue.
BUG=b:477096462
TEST=Build Pass, Bootup OK and Suspend/Resume OK
Change-Id: I33ebbac0dd6d0d0d352697c14de9ecef28ba08cb
Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Provide an optional, coreboot-managed CBMEM scratch buffer for SMM code.
CBMEM is reserved from the OS via the memory map and persists across S3,
so it is suitable for firmware-owned DMA buffers used during resume.
SMRAM is not device DMA-accessible, so this scratch buffer must live
outside SMRAM.
Pass the base/size to SMM via smm_runtime so SMM code can validate
placement and avoid relying on untrusted pointers.
The CBMEM region size is configurable via SMM_OPAL_S3_SCRATCH_SIZE,
defaulting to 16 KiB as a safe value.
TEST=tested with rest of patch train
Change-Id: I79ae5327f27e574b151b7cf456761fa0d7038f2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
As directory was copied from genoa_poc, we need to adjust headers to
correspond to phoenix_poc repository.
Change-Id: Id3aeaf6ecf138ea94282ae2a308a45c77ff73b02
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91481
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on genoa_poc, this patch adds directory structure for Phoenix
OpenSIL as well as git submodule needed to build it.
Subsequent patches will begin adjusting this directory to Phoenix (Zen4)
silicon.
Change-Id: I04de276c1567c20d1e852efe220efa8131f53843
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91480
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Sunrise Point-LP PCH built into the Google Pixelbook Eve suffers
from an erratum where the "CLKREQ# asserted to clock active timing" may
exceed the maximum specification, resulting in exit instability from
ASPM L1 state.
This is documented in erratum 47 of the "Intel 100 Series and C230
Series Chipset Family Platform Controller Hub Specification Update"
(Revision 015, December 2018):
https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf
The Specification Update constrains applicability of the erratum to
Endpoints which do not support LTR or advertise an LTR value of less
than 1 usec. The reason is that the PCH needs about 1 usec for the
clock to become active after CLKREQ# asserted. For devices without LTR
support, the maximum is 400 nsec (T_CRLon, PCIe CEM r6.0.1 sec 2.11.2).
The Pixelbook Eve has an Intel 7265 Stone Peak wifi card attached to
Root Port 1. It seems this wifi card triggers the erratum: There are
several reports that the wifi card is no longer usable since commit
torvalds/linux@4d4c10f763 ("PCI: Explicitly put devices into D0 when
initializing").
Briefly, coreboot enables all ASPM features on boot, the kernel used to
disable certain ASPM features prior to the commit, now no longer does
and the erratum is thus exposed. (The commit changed the cached power
state of the wifi card from PCI_UNKNOWN to PCI_D0, which now causes
pcie_config_aspm_link() to no longer disable L1 PCI PM.)
Apply the recommended workaround, which is to disable the associated PCH
CLKREQ# signal to keep the PCIe clock active during L1.
BUG=https://github.com/MrChromebox/firmware/issues/786
TEST=https://bugzilla.kernel.org/show_bug.cgi?id=220705#c31
Change-Id: I00c6555c2b93f46971ea8e4344f8990f86b03a3d
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
On Skylake mainboards, enablement of the Source Clock of a PCIe Root
Port is currently dependent on enablement of CLKREQ# in the devicetree.
However it may be desirable to disable CLKREQ# but still keep the Source
Clock enabled. Specifically, that's the recommended workaround for
erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from
ASPM L1 state:
"disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock
active during L1"
https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf
Therefore, key Source Clock enablement off of Root Port enablement in
the devicetree, rather than CLKREQ# enablement. A subsequent commit
takes advantage of this to implement the workaround on Google Pixelbook
Eve mainboards.
Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure "cpu_ratio_override" to 0x20 (32) for the Fatcat baseboard.
This ensures the Panther Lake SoC initializes with the correct
base frequency ratio to meet the performance and thermal targets
defined for this hardware revision.
BUG=none
BRANCH=none
TEST=Build and boot Fatcat; verify CPU base frequency has updated.
Change-Id: I7ea6c7dccaf731bab1256b3297d83518ceea532c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91648
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Additionally, guard USB camera GPIO enablement using dedicated
Kconfig option.
This reverts commit bbbc655b15.
Reason for revert: FW should enable the GPIO_USB_CAM_ENABLE (206).
Change-Id: I7966240939c51a4be7027debb0a66d3e11cb75cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Replace checked-in .spd.hex blobs with .spd.json attribute descriptions
and generate the .spd.hex at build time via spd_gen.
Change-Id: I777b12df911576c684ee8146f5ec69e61b0cc772
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91292
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
