nb/intel/haswell: Enable SA clock gating later

Reference code version 1.9.1 sets `SAPMCTL` bit 0 just before setting
`BIOS_RESET_CPL` bits 0 and 1. Do the same thing in coreboot.

Change-Id: I36e24d2a3bd754e56df59a1e996d285ec6bf5205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91632
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>

src/northbridge/intel/haswell/early_init.c

@@ -72,10 +72,6 @@ static void haswell_setup_misc(void)
 	reg32 |= (1 << 9) | (1 << 10);
 	mchbar_write32(SAPMCTL, reg32);
 
-	/* Enable SA Clock Gating */
-	reg32 = mchbar_read32(SAPMCTL);
-	mchbar_write32(SAPMCTL, reg32 | 1);
-
 	reg32 = mchbar_read32(INTRDIRCTL);
 	reg32 |= (1 << 4) | (1 << 5);
 	mchbar_write32(INTRDIRCTL, reg32);

src/northbridge/intel/haswell/northbridge.c

@@ -464,6 +464,9 @@ static void northbridge_init(struct device *dev)
 
 	disable_devices();
 
+	/* Enable SA Clock Gating */
+	mchbar_setbits32(SAPMCTL, 1 << 0);
+
 	/*
 	 * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
 	 * that BIOS has initialized memory and power management.