nb/intel/haswell: Move early PEG stuff to separate file
Only Haswell / Broadwell Trad have PEG devices. So, don't include PEG-related code when building for Haswell / Broadwell ULT. Change-Id: I478f5c6d5850e6fb7cecc04ae5e2aae51d20fc92 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Angel Pons
Matt DeVillier
parent
76290e8cdc
commit
fed6f9494d
5 changed files with 93 additions and 77 deletions
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@ -20,6 +20,10 @@ romstage-y += raminit_shared.c
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postcar-y += memmap.c
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ifneq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += early_peg.c
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endif
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ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
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romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
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subdirs-y += native_raminit
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@ -8,8 +8,6 @@
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#include "haswell.h"
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static bool peg_hidden[MAX_PEG_FUNC];
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static void haswell_setup_bars(void)
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{
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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@ -64,78 +62,6 @@ static void haswell_setup_igd(void)
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pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
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}
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static void start_peg2_link_training(const pci_devfn_t dev)
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{
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u32 mask;
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switch (dev) {
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case PCI_DEV(0, 1, 2):
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mask = DEVEN_D1F2EN;
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break;
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case PCI_DEV(0, 1, 1):
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mask = DEVEN_D1F1EN;
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break;
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case PCI_DEV(0, 1, 0):
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mask = DEVEN_D1F0EN;
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break;
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default:
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printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
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return;
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}
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pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
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printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
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/*
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* The MRC will perform PCI enumeration, and if it detects a VGA
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* device in a PEG slot, it will disable the IGD and not reserve
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* any memory for it. Since the memory map is locked by the time
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* MRC finishes, the IGD can't be enabled afterwards. Wonderful.
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*
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* If one really wants to enable the Intel iGPU as primary, hide
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* all PEG devices during MRC execution. This will trick the MRC
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* into thinking there aren't any, and will enable the IGD. Note
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* that PEG AFE settings will not be programmed, which may cause
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* stability problems at higher PCIe link speeds. The most ideal
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* way to fix this problem for good is to implement native init.
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*/
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if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
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pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
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peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
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printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
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PCI_FUNC(PCI_DEV2DEVFN(dev)));
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}
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}
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void haswell_unhide_peg(void)
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{
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u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
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for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
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if (peg_hidden[fn]) {
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deven |= DEVEN_D1F0EN >> fn;
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peg_hidden[fn] = false;
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printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
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}
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}
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pci_write_config32(HOST_BRIDGE, DEVEN, deven);
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}
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static void haswell_setup_peg(void)
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{
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u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
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if (deven & DEVEN_D1F2EN)
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start_peg2_link_training(PCI_DEV(0, 1, 2));
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if (deven & DEVEN_D1F1EN)
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start_peg2_link_training(PCI_DEV(0, 1, 1));
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if (deven & DEVEN_D1F0EN)
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start_peg2_link_training(PCI_DEV(0, 1, 0));
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}
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static void haswell_setup_misc(void)
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{
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u32 reg32;
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@ -188,7 +114,9 @@ void haswell_early_initialization(void)
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/* Setup IOMMU BARs */
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haswell_setup_iommu();
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haswell_setup_peg();
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if (!CONFIG(INTEL_LYNXPOINT_LP))
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northbridge_setup_peg();
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haswell_setup_igd();
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haswell_setup_misc();
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81
src/northbridge/intel/haswell/early_peg.c
Normal file
81
src/northbridge/intel/haswell/early_peg.c
Normal file
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@ -0,0 +1,81 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <types.h>
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static bool peg_hidden[MAX_PEG_FUNC];
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static void start_peg2_link_training(const pci_devfn_t dev)
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{
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u32 mask;
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switch (dev) {
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case PCI_DEV(0, 1, 2):
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mask = DEVEN_D1F2EN;
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break;
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case PCI_DEV(0, 1, 1):
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mask = DEVEN_D1F1EN;
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break;
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case PCI_DEV(0, 1, 0):
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mask = DEVEN_D1F0EN;
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break;
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default:
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printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
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return;
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}
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pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
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printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
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/*
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* The MRC will perform PCI enumeration, and if it detects a VGA
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* device in a PEG slot, it will disable the IGD and not reserve
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* any memory for it. Since the memory map is locked by the time
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* MRC finishes, the IGD can't be enabled afterwards. Wonderful.
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*
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* If one really wants to enable the Intel iGPU as primary, hide
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* all PEG devices during MRC execution. This will trick the MRC
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* into thinking there aren't any, and will enable the IGD. Note
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* that PEG AFE settings will not be programmed, which may cause
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* stability problems at higher PCIe link speeds. The most ideal
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* way to fix this problem for good is to implement native init.
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*/
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if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
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pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
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peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
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printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
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PCI_FUNC(PCI_DEV2DEVFN(dev)));
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}
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}
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void northbridge_unhide_peg(void)
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{
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u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
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for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
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if (peg_hidden[fn]) {
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deven |= DEVEN_D1F0EN >> fn;
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peg_hidden[fn] = false;
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printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
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}
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}
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pci_write_config32(HOST_BRIDGE, DEVEN, deven);
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}
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void northbridge_setup_peg(void)
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{
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u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
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if (deven & DEVEN_D1F2EN)
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start_peg2_link_training(PCI_DEV(0, 1, 2));
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if (deven & DEVEN_D1F1EN)
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start_peg2_link_training(PCI_DEV(0, 1, 1));
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if (deven & DEVEN_D1F0EN)
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start_peg2_link_training(PCI_DEV(0, 1, 0));
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}
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@ -37,7 +37,9 @@ void mb_late_romstage_setup(void); /* optional */
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void haswell_early_initialization(void);
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void haswell_late_initialization(void);
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void haswell_unhide_peg(void);
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void northbridge_setup_peg(void);
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void northbridge_unhide_peg(void);
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void dmi_early_init(void);
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void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
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@ -56,7 +56,8 @@ void mainboard_romstage_entry(void)
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txt_dump_regions();
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}
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haswell_unhide_peg();
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if (!CONFIG(INTEL_LYNXPOINT_LP))
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northbridge_unhide_peg();
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romstage_handoff_init(s3resume);
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