nb/intel/broadwell: Clean up cosmetics
Yes, the "Coding Style" page of the coreboot docs states the following:
Bulk style changes to existing code ("cleanup patches") should
avoid changing existing style choices unless they actually
violate this style guide, or there is broad consensus that the
new version is an improvement. By default the style choices of
the original author should be honored.
However, when attempting to unify two codebases (Haswell and Broadwell),
style differences only make it harder to find the functional differences
between the codebases. So, it makes sense to unify the code style first,
so that only functional differences remain. Especially if these cosmetic
alignment changes are reproducible, i.e. they don't change the resulting
coreboot.rom when using `make BUILD_TIMELESS=1` to build.
Sort includes alphabetically, unbreak some long lines that are less than
96 characters long, combine variable declaration and initialisation, use
C-style comments, use one line for printk strings (easier to use grep to
find them this way), constify some values the compiler already knew they
were constant (they get inlined anyway), remove unnecessary parentheses,
fix space usage around operators, align some comments with Haswell code,
rename a few things for consistency with Haswell, use an early return in
place of an if-block (like Haswell does), drop a few unused includes and
include `types.h` from files that need it.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I872068e93f1960d90a914193ccb346fc77652220
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91620
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Angel Pons
Matt DeVillier
parent
53bc76856c
commit
31f4c30a08
12 changed files with 193 additions and 247 deletions
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@ -4,7 +4,7 @@
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#define _SOC_INTEL_BROADWELL_CHIP_H_
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#include <drivers/intel/gma/gma.h>
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#include <stdint.h>
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#include <types.h>
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struct northbridge_intel_broadwell_config {
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/*
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@ -30,29 +30,28 @@ static void broadwell_setup_bars(void)
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void systemagent_early_init(void)
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{
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const bool vtd_capable =
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!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
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const bool vtd_capable = !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
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broadwell_setup_bars();
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/* Device enable: IGD and Mini-HD */
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pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
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if (vtd_capable) {
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/* setup BARs: zeroize top 32 bits; set enable bit */
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mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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if (!vtd_capable)
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return;
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/* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */
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u32 reg32;
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reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
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write32p(GFXVT_BASE_ADDRESS + ARCHDIS,
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reg32 | DMAR_LCKDN | PRSCAPDIS);
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/* lock VTVC0BAR policy cfg registers */
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reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS);
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write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
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reg32 | DMAR_LCKDN);
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}
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/* Setup BARs: zeroize top 32 bits; set enable bit */
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mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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/* Set PRSCAPDIS, lock GFXVTBAR policy config registers */
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u32 reg32;
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reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
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write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | PRSCAPDIS);
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/* lock VTVC0BAR policy cfg registers */
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reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS);
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write32p(VTVC0_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN);
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}
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <bootmode.h>
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@ -11,20 +10,20 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <string.h>
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#include <reg_script.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <drivers/intel/gma/libgfxinit.h>
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#include <drivers/intel/gma/opregion.h>
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#include <soc/pm.h>
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#include <soc/systemagent.h>
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#include <reg_script.h>
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#include <northbridge/intel/broadwell/chip.h>
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#include <security/vboot/vbnv.h>
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#include <soc/igd.h>
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#include <soc/pm.h>
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#include <soc/systemagent.h>
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#include <string.h>
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#include <types.h>
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#define GT_RETRY 1000
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#define GTT_RETRY 1000
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enum {
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GT_CDCLK_DEFAULT = 0,
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GT_CDCLK_337,
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@ -43,7 +42,7 @@ struct reg_script haswell_early_init_script[] = {
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/* Enable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
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/* Enable Counters */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
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@ -104,10 +103,10 @@ struct reg_script haswell_early_init_script[] = {
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
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/* Set RC6 VIDs */
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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@ -127,13 +126,12 @@ static const struct reg_script haswell_late_init_script[] = {
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/* Disable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
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/* Enable power well for DP and Audio */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
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(1 << 30), (1 << 30), GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 30), (1 << 30), GTT_RETRY),
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REG_SCRIPT_END
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};
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@ -141,7 +139,7 @@ static const struct reg_script haswell_late_init_script[] = {
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static const struct reg_script broadwell_early_init_script[] = {
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/* Enable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
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/* Enable push bus metric control and shift */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
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@ -206,10 +204,10 @@ static const struct reg_script broadwell_early_init_script[] = {
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
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/* Set RC6 VIDs */
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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@ -228,12 +226,11 @@ static const struct reg_script broadwell_late_init_script[] = {
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/* Disable Force Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
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/* Enable power well for DP and Audio */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
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(1 << 30), (1 << 30), GT_RETRY),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 30), (1 << 30), GTT_RETRY),
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REG_SCRIPT_END
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};
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@ -269,7 +266,8 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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}
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int gtt_poll(u32 reg, u32 mask, u32 value)
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{ unsigned int try = GT_RETRY;
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{
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unsigned int try = GTT_RETRY;
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u32 data;
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while (try--) {
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@ -322,13 +320,16 @@ static void gma_setup_panel(struct device *dev)
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gtt_write(PCH_PP_DIVISOR, reg32);
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}
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/* So far all devices seem to use the PCH PWM function.
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The CPU PWM registers are all zero after reset. */
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/*
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* So far all devices seem to use the PCH PWM function.
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* The CPU PWM registers are all zero after reset.
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*/
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if (panel_cfg->backlight_pwm_hz) {
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/* For Lynx Point-LP:
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Reference clock is 24MHz. We can choose either a 16
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or a 128 step increment. Use 16 if we would have less
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than 100 steps otherwise. */
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/*
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* For Lynx Point-LP:
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* Reference clock is 24MHz. We can choose either a 16 or a 128 step
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* increment. Use 16 if we would have less than 100 steps otherwise.
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*/
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const unsigned int refclock = 24 * MHz;
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const unsigned int hz_limit = refclock / 128 / 100;
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unsigned int pwm_increment, pwm_period;
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@ -350,7 +351,7 @@ static void gma_setup_panel(struct device *dev)
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refclock / MHz, pwm_increment, pwm_period,
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DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period));
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/* Start with a 50% duty cycle. */
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/* Start with a 50% duty cycle */
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gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
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gtt_write(BLC_PWM_PCH_CTL1,
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@ -382,8 +383,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, bool *const inform_pc,
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*/
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if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
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cdclk = GT_CDCLK_337;
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else if (gpu_is_ulx || cpu_is_ult ||
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cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
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else if (gpu_is_ulx || cpu_is_ult || cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
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cdclk = GT_CDCLK_450;
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else
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cdclk = GT_CDCLK_540;
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@ -429,8 +429,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, bool *const inform_pc,
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*/
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if (cdclk == GT_CDCLK_337)
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cdclk = GT_CDCLK_337;
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else if (cdclk == GT_CDCLK_450 ||
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(gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
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else if (cdclk == GT_CDCLK_450 || (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
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cdclk = GT_CDCLK_450;
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else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
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(cpu_is_ult && cdclk == GT_CDCLK_DEFAULT))
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@ -501,7 +500,7 @@ static void igd_cdclk_init(struct device *dev, const bool is_broadwell)
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gtt_rmw(0x64810, 0xfffff800, dpdiv);
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}
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static void igd_init(struct device *dev)
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static void gma_init(struct device *dev)
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{
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bool is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
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u32 rp1_gfx_freq;
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@ -582,11 +581,11 @@ static void gma_generate_ssdt(const struct device *dev)
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drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
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}
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static struct device_operations igd_ops = {
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static struct device_operations gma_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = igd_init,
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.init = gma_init,
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.acpi_fill_ssdt = gma_generate_ssdt,
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.ops_pci = &pci_dev_ops_pci,
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};
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@ -606,7 +605,7 @@ static const unsigned short pci_device_ids[] = {
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};
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static const struct pci_driver igd_driver __pci_driver = {
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.ops = &igd_ops,
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.vendor = PCI_VID_INTEL,
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.ops = &gma_ops,
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.vendor = PCI_VID_INTEL,
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.devices = pci_device_ids,
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};
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@ -7,9 +7,8 @@
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typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
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static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
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uint16_t length, uint8_t enable,
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uint8_t oc_pin, uint8_t location)
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static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, uint16_t length,
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uint8_t enable, uint8_t oc_pin, uint8_t location)
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{
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pei_data->usb2_ports[port].length = length;
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pei_data->usb2_ports[port].enable = enable;
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@ -17,9 +16,8 @@ static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
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pei_data->usb2_ports[port].location = location;
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}
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static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
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uint8_t enable, uint8_t oc_pin,
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uint8_t fixed_eq)
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static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, uint8_t enable,
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uint8_t oc_pin, uint8_t fixed_eq)
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{
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pei_data->usb3_ports[port].enable = enable;
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pei_data->usb3_ports[port].oc_pin = oc_pin;
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@ -10,7 +10,7 @@
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include <stdint.h>
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#include <types.h>
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static uintptr_t dpr_region_start(void)
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{
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@ -52,6 +52,5 @@ void fill_postcar_frame(struct postcar_frame *pcf)
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* with different TSEG size configurations.
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*/
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const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
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}
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@ -2,18 +2,17 @@
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#include <console/console.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <acpi/acpi.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/refcode.h>
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#include <soc/systemagent.h>
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#include <types.h>
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u8 systemagent_revision(void)
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{
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@ -21,8 +20,7 @@ u8 systemagent_revision(void)
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return pci_read_config8(sa_dev, PCI_REVISION_ID);
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}
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static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
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u32 *len)
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static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 pciexbar_reg;
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|
|
@ -35,20 +33,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
|
|||
return 0;
|
||||
|
||||
switch ((pciexbar_reg >> 1) & 3) {
|
||||
case 0: // 256MB
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
|
||||
(1 << 28));
|
||||
*len = 256 * 1024 * 1024;
|
||||
case 0: /* 256 MiB */
|
||||
*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 | 1 << 28);
|
||||
*len = 256 * MiB;
|
||||
return 1;
|
||||
case 1: // 128M
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
|
||||
(1 << 28)|(1 << 27));
|
||||
*len = 128 * 1024 * 1024;
|
||||
case 1: /* 128M */
|
||||
*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | 1 << 27);
|
||||
*len = 128 * MiB;
|
||||
return 1;
|
||||
case 2: // 64M
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
|
||||
(1 << 28)|(1 << 27)|(1 << 26));
|
||||
*len = 64 * 1024 * 1024;
|
||||
case 2: /* 64M */
|
||||
*base = pciexbar_reg & (1 << 31 | 1 << 30 | 1 << 29 |
|
||||
1 << 28 | 1 << 27 | 1 << 26);
|
||||
*len = 64 * MiB;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -57,35 +53,31 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
|
|||
|
||||
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
|
||||
{
|
||||
u32 bar;
|
||||
u32 bar = pci_read_config32(dev, index);
|
||||
|
||||
bar = pci_read_config32(dev, index);
|
||||
|
||||
/* If not enabled don't report it. */
|
||||
/* If not enabled don't report it */
|
||||
if (!(bar & 0x1))
|
||||
return 0;
|
||||
|
||||
/* Knock down the enable bit. */
|
||||
/* Knock down the enable bit */
|
||||
*base = bar & ~1;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* There are special BARs that actually are programmed in the MCHBAR. These
|
||||
* Intel special features, but they do consume resources that need to be
|
||||
* accounted for. */
|
||||
static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
|
||||
u32 *len)
|
||||
/*
|
||||
* There are special BARs that actually are programmed in the MCHBAR. These Intel special
|
||||
* features, but they do consume resources that need to be accounted for.
|
||||
*/
|
||||
static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
|
||||
{
|
||||
u32 bar;
|
||||
u32 bar = mchbar_read32(index);
|
||||
|
||||
bar = mchbar_read32(index);
|
||||
|
||||
/* If not enabled don't report it. */
|
||||
/* If not enabled don't report it */
|
||||
if (!(bar & 0x1))
|
||||
return 0;
|
||||
|
||||
/* Knock down the enable bit. */
|
||||
/* Knock down the enable bit */
|
||||
*base = bar & ~1;
|
||||
|
||||
return 1;
|
||||
|
|
@ -94,8 +86,7 @@ static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
|
|||
struct fixed_mmio_descriptor {
|
||||
unsigned int index;
|
||||
u32 size;
|
||||
int (*get_resource)(struct device *dev, unsigned int index,
|
||||
u32 *base, u32 *size);
|
||||
int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size);
|
||||
const char *description;
|
||||
};
|
||||
|
||||
|
|
@ -108,10 +99,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
|
|||
{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
|
||||
};
|
||||
|
||||
/*
|
||||
* Add all known fixed MMIO ranges that hang off the host bridge/memory
|
||||
* controller device.
|
||||
*/
|
||||
/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
|
||||
static void mc_add_fixed_mmio_resources(struct device *dev)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -124,23 +112,22 @@ static void mc_add_fixed_mmio_resources(struct device *dev)
|
|||
|
||||
size = mc_fixed_resources[i].size;
|
||||
index = mc_fixed_resources[i].index;
|
||||
if (!mc_fixed_resources[i].get_resource(dev, index,
|
||||
&base, &size))
|
||||
if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size))
|
||||
continue;
|
||||
|
||||
resource = new_resource(dev, mc_fixed_resources[i].index);
|
||||
resource->base = base;
|
||||
resource->size = size;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
|
||||
IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
|
||||
printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
|
||||
__func__, mc_fixed_resources[i].description, index,
|
||||
(unsigned long)base, (unsigned long)(base + size - 1));
|
||||
}
|
||||
}
|
||||
|
||||
/* Host Memory Map:
|
||||
/*
|
||||
* Host Memory Map:
|
||||
*
|
||||
* +--------------------------+ TOUUD
|
||||
* | |
|
||||
|
|
@ -153,13 +140,15 @@ static void mc_add_fixed_mmio_resources(struct device *dev)
|
|||
* +--------------------------+ BGSM
|
||||
* | TSEG |
|
||||
* +--------------------------+ TSEGMB
|
||||
* | DPR |
|
||||
* +--------------------------+ (DPR top - DPR size)
|
||||
* | Usage DRAM |
|
||||
* +--------------------------+ 0
|
||||
*
|
||||
* Some of the base registers above can be equal making the size of those
|
||||
* regions 0. The reason is because the memory controller internally subtracts
|
||||
* the base registers from each other to determine sizes of the regions. In
|
||||
* other words, the memory map is in a fixed order no matter what.
|
||||
* Some of the base registers above can be equal, making the size of the regions within 0.
|
||||
* This is because the memory controller internally subtracts the base registers from each
|
||||
* other to determine sizes of the regions. In other words, the memory map regions are always
|
||||
* in a fixed order, no matter what sizes they have.
|
||||
*/
|
||||
|
||||
struct map_entry {
|
||||
|
|
@ -169,17 +158,12 @@ struct map_entry {
|
|||
const char *description;
|
||||
};
|
||||
|
||||
static void read_map_entry(struct device *dev, struct map_entry *entry,
|
||||
uint64_t *result)
|
||||
static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)
|
||||
{
|
||||
uint64_t value;
|
||||
uint64_t mask;
|
||||
/* All registers are on a 1MiB granularity */
|
||||
const uint64_t mask = ~((1ULL << 20) - 1);
|
||||
|
||||
/* All registers are on a 1MiB granularity. */
|
||||
mask = ((1ULL<<20)-1);
|
||||
mask = ~mask;
|
||||
|
||||
value = 0;
|
||||
uint64_t value = 0;
|
||||
|
||||
if (entry->is_64_bit) {
|
||||
value = pci_read_config32(dev, entry->reg + 4);
|
||||
|
|
@ -203,12 +187,9 @@ static void read_map_entry(struct device *dev, struct map_entry *entry,
|
|||
.description = desc_, \
|
||||
}
|
||||
|
||||
#define MAP_ENTRY_BASE_64(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 1, 0, desc_)
|
||||
#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 1, 1, desc_)
|
||||
#define MAP_ENTRY_BASE_32(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 0, 0, desc_)
|
||||
#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
|
||||
#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
|
||||
#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
|
||||
|
||||
enum {
|
||||
TOM_REG,
|
||||
|
|
@ -221,59 +202,55 @@ enum {
|
|||
BGSM_REG,
|
||||
BDSM_REG,
|
||||
TSEG_REG,
|
||||
// Must be last.
|
||||
NUM_MAP_ENTRIES
|
||||
/* Must be last */
|
||||
NUM_MAP_ENTRIES,
|
||||
};
|
||||
|
||||
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
|
||||
[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
|
||||
[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
|
||||
[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
|
||||
[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
|
||||
[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
|
||||
[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
|
||||
[MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
|
||||
[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
|
||||
[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
|
||||
[REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
|
||||
[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
|
||||
[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
|
||||
[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
|
||||
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
|
||||
[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
|
||||
[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
|
||||
[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
|
||||
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"),
|
||||
};
|
||||
|
||||
static void mc_read_map_entries(struct device *dev, uint64_t *values)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < NUM_MAP_ENTRIES; i++)
|
||||
for (int i = 0; i < NUM_MAP_ENTRIES; i++)
|
||||
read_map_entry(dev, &memory_map[i], &values[i]);
|
||||
}
|
||||
|
||||
static void mc_report_map_entries(struct device *dev, uint64_t *values)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
|
||||
for (int i = 0; i < NUM_MAP_ENTRIES; i++) {
|
||||
printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
|
||||
memory_map[i].description, values[i]);
|
||||
}
|
||||
/* One can validate the BDSM and BGSM against the GGC. */
|
||||
/* One can validate the BDSM and BGSM against the GGC */
|
||||
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
|
||||
}
|
||||
|
||||
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
|
||||
{
|
||||
unsigned long index;
|
||||
uint64_t mc_values[NUM_MAP_ENTRIES];
|
||||
unsigned long dpr_size = 0;
|
||||
u32 dpr_reg;
|
||||
|
||||
/* Read in the MAP registers and report their values. */
|
||||
mc_read_map_entries(dev, &mc_values[0]);
|
||||
mc_report_map_entries(dev, &mc_values[0]);
|
||||
/* Read in the MAP registers and report their values */
|
||||
mc_read_map_entries(dev, mc_values);
|
||||
mc_report_map_entries(dev, mc_values);
|
||||
|
||||
/*
|
||||
* DMA Protected Range can be reserved below TSEG for PCODE patch
|
||||
* or TXT/Boot Guard related data. Rather than report a base address
|
||||
* or TXT/Boot Guard related data. Rather than report a base address,
|
||||
* the DPR register reports the TOP of the region, which is the same
|
||||
* as TSEG base. The region size is reported in MiB in bits 11:4.
|
||||
* as TSEG base. The region size is reported in MiB in bits 11:4.
|
||||
*/
|
||||
dpr_reg = pci_read_config32(dev, DPR);
|
||||
u32 dpr_reg = pci_read_config32(dev, DPR);
|
||||
unsigned long dpr_size = 0;
|
||||
if (dpr_reg & DPR_EPM) {
|
||||
dpr_size = (dpr_reg & DPR_SIZE_MASK) << 26;
|
||||
printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
|
||||
|
|
@ -281,36 +258,31 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
|
|||
|
||||
/*
|
||||
* These are the host memory ranges that should be added:
|
||||
* - 0 -> 0xa0000: cacheable
|
||||
* - 0xc0000 -> TSEG : cacheable
|
||||
* - TESG -> BGSM: cacheable with standard MTRRs and reserved
|
||||
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
|
||||
* - 4GiB -> TOUUD: cacheable
|
||||
* - 0 -> 0xa0000: cacheable
|
||||
* - 0xc0000 -> TSEG: cacheable
|
||||
* - TSEG -> BGSM: cacheable with standard MTRRs and reserved
|
||||
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
|
||||
* - 4GiB -> TOUUD: cacheable
|
||||
*
|
||||
* The default SMRAM space is reserved so that the range doesn't
|
||||
* have to be saved during S3 Resume. Once marked reserved the OS
|
||||
* cannot use the memory. This is a bit of an odd place to reserve
|
||||
* the region, but the CPU devices don't have dev_ops->read_resources()
|
||||
* called on them.
|
||||
* The default SMRAM space is reserved so that the range doesn't have to be saved
|
||||
* during S3 Resume. Once marked reserved the OS cannot use the memory. This is a
|
||||
* bit of an odd place to reserve the region, but the CPU devices don't have
|
||||
* dev_ops->read_resources() called on them.
|
||||
*
|
||||
* The range 0xa0000 -> 0xc0000 does not have any resources
|
||||
* associated with it to handle legacy VGA memory. If this range
|
||||
* is not omitted the mtrr code will setup the area as cacheable
|
||||
* causing VGA access to not work.
|
||||
* The range 0xa0000 -> 0xc0000 does not have any resources associated with it to
|
||||
* handle legacy VGA memory. If this range is not omitted the mtrr code will setup
|
||||
* the area as cacheable, causing VGA access to not work.
|
||||
*
|
||||
* The TSEG region is mapped as cacheable so that one can perform
|
||||
* SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
|
||||
* precedence over the existing MTRRs covering this region.
|
||||
* The TSEG region is mapped as cacheable so that one can perform SMRAM relocation
|
||||
* faster. Once the SMRR is enabled, the SMRR takes precedence over the existing
|
||||
* MTRRs covering this region.
|
||||
*
|
||||
* It should be noted that cacheable entry types need to be added in
|
||||
* order. The reason is that the current MTRR code assumes this and
|
||||
* falls over itself if it isn't.
|
||||
* It should be noted that cacheable entry types need to be added in order. The reason
|
||||
* is that the current MTRR code assumes this and falls over itself if it isn't.
|
||||
*
|
||||
* The resource index starts low and should not meet or exceed
|
||||
* PCI_BASE_ADDRESS_0.
|
||||
* The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0.
|
||||
*/
|
||||
index = *resource_cnt;
|
||||
|
||||
unsigned long index = *resource_cnt;
|
||||
|
||||
/*
|
||||
* 0 - > 0xa0000: RAM
|
||||
|
|
@ -339,22 +311,21 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
|
|||
static void systemagent_read_resources(struct device *dev)
|
||||
{
|
||||
int index = 0;
|
||||
const bool vtd_capable =
|
||||
!(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
|
||||
const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
|
||||
|
||||
/* Read standard PCI resources. */
|
||||
/* Read standard PCI resources */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add all fixed MMIO resources. */
|
||||
/* Add all fixed MMIO resources */
|
||||
mc_add_fixed_mmio_resources(dev);
|
||||
|
||||
/* Add VT-d MMIO resources if capable */
|
||||
/* Add VT-d MMIO resources, if capable */
|
||||
if (vtd_capable) {
|
||||
mmio_range(dev, index++, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE);
|
||||
mmio_range(dev, index++, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE);
|
||||
}
|
||||
|
||||
/* Calculate and add DRAM resources. */
|
||||
/* Calculate and add DRAM resources */
|
||||
mc_add_dram_resources(dev, &index);
|
||||
}
|
||||
|
||||
|
|
@ -364,8 +335,8 @@ static void systemagent_init(struct device *dev)
|
|||
mchbar_clrsetbits8(MCH_PAIR, 0x7, 0x4); /* Clear 2:0, set Fixed Priority */
|
||||
|
||||
/*
|
||||
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
|
||||
* that BIOS has initialized memory and power management
|
||||
* Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
|
||||
* that BIOS has initialized memory and power management.
|
||||
*/
|
||||
mchbar_setbits8(BIOS_RESET_CPL, 3);
|
||||
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
|
||||
|
|
@ -398,11 +369,11 @@ static const struct pci_driver systemagent_driver __pci_driver = {
|
|||
};
|
||||
|
||||
struct device_operations broadwell_pci_domain_ops = {
|
||||
.read_resources = &pci_domain_read_resources,
|
||||
.set_resources = &pci_domain_set_resources,
|
||||
.scan_bus = &pci_host_bridge_scan_bus,
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.scan_bus = pci_host_bridge_scan_bus,
|
||||
#if CONFIG(HAVE_ACPI_TABLES)
|
||||
.write_acpi_tables = &northbridge_write_acpi_tables,
|
||||
.write_acpi_tables = northbridge_write_acpi_tables,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -413,5 +384,5 @@ static void broadwell_init_pre_device(void *chip_info)
|
|||
|
||||
struct chip_operations northbridge_intel_broadwell_ops = {
|
||||
.name = "Intel Broadwell",
|
||||
.init = &broadwell_init_pre_device,
|
||||
.init = broadwell_init_pre_device,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,10 +2,10 @@
|
|||
|
||||
#include <console/streams.h>
|
||||
#include <device/device.h>
|
||||
#include <northbridge/intel/broadwell/chip.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <northbridge/intel/broadwell/chip.h>
|
||||
#include <static.h>
|
||||
|
||||
static void ABI_X86 send_to_console(unsigned char b)
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
#include <memory_info.h>
|
||||
#include <mrc_cache.h>
|
||||
#include <string.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <soc/pm.h>
|
||||
|
|
@ -84,25 +83,19 @@ static void report_memory_config(void)
|
|||
*/
|
||||
static void sdram_initialize(struct pei_data *pei_data)
|
||||
{
|
||||
size_t mrc_size;
|
||||
pei_wrapper_entry_t entry;
|
||||
int ret;
|
||||
|
||||
broadwell_fill_pei_data(pei_data);
|
||||
|
||||
/* Assume boot device is memory mapped. */
|
||||
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
|
||||
|
||||
pei_data->saved_data =
|
||||
mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
|
||||
&mrc_size);
|
||||
size_t mrc_size;
|
||||
pei_data->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, &mrc_size);
|
||||
if (pei_data->saved_data) {
|
||||
/* MRC cache found */
|
||||
pei_data->saved_data_size = mrc_size;
|
||||
} else if (pei_data->boot_mode == ACPI_S3) {
|
||||
/* Waking from S3 and no cache. */
|
||||
printk(BIOS_DEBUG,
|
||||
"No MRC cache found in S3 resume path.\n");
|
||||
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
|
||||
post_code(POSTCODE_RESUME_FAILURE);
|
||||
system_reset();
|
||||
} else {
|
||||
|
|
@ -110,7 +103,7 @@ static void sdram_initialize(struct pei_data *pei_data)
|
|||
}
|
||||
|
||||
/*
|
||||
* Do not use saved pei data. Can be set by mainboard romstage
|
||||
* Do not use saved pei data. Can be set by mainboard romstage
|
||||
* to force a full train of memory on every boot.
|
||||
*/
|
||||
if (pei_data->disable_saved_data) {
|
||||
|
|
@ -120,13 +113,13 @@ static void sdram_initialize(struct pei_data *pei_data)
|
|||
}
|
||||
|
||||
/* We don't care about leaking the mapping */
|
||||
entry = cbfs_ro_map("mrc.bin", NULL);
|
||||
pei_wrapper_entry_t entry = cbfs_ro_map("mrc.bin", NULL);
|
||||
if (entry == NULL)
|
||||
die("mrc.bin not found!");
|
||||
|
||||
printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
|
||||
|
||||
ret = entry(pei_data);
|
||||
int ret = entry(pei_data);
|
||||
if (ret < 0)
|
||||
die("pei_data version mismatch\n");
|
||||
|
||||
|
|
@ -141,10 +134,8 @@ static void sdram_initialize(struct pei_data *pei_data)
|
|||
|
||||
static void setup_sdram_meminfo(struct pei_data *pei_data)
|
||||
{
|
||||
struct memory_info *mem_info;
|
||||
|
||||
printk(BIOS_DEBUG, "create cbmem for dimm information\n");
|
||||
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
|
||||
struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
|
||||
|
||||
if (!mem_info) {
|
||||
printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n");
|
||||
|
|
@ -156,8 +147,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
|
|||
mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt;
|
||||
for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) {
|
||||
struct dimm_info *dimm = &mem_info->dimm[i];
|
||||
const struct pei_dimm_info *pei_dimm =
|
||||
&pei_data->meminfo.dimm[i];
|
||||
const struct pei_dimm_info *pei_dimm = &pei_data->meminfo.dimm[i];
|
||||
dimm->dimm_size = pei_dimm->dimm_size;
|
||||
dimm->ddr_type = pei_dimm->ddr_type;
|
||||
dimm->ddr_frequency = pei_dimm->ddr_frequency;
|
||||
|
|
@ -167,8 +157,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
|
|||
dimm->bank_locator = pei_dimm->bank_locator;
|
||||
memcpy(&dimm->serial, &pei_dimm->serial,
|
||||
MIN(sizeof(dimm->serial), sizeof(pei_dimm->serial)));
|
||||
memcpy(&dimm->module_part_number,
|
||||
&pei_dimm->module_part_number,
|
||||
memcpy(&dimm->module_part_number, &pei_dimm->module_part_number,
|
||||
MIN(sizeof(dimm->module_part_number),
|
||||
sizeof(pei_dimm->module_part_number)));
|
||||
dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
|
||||
|
|
|
|||
|
|
@ -21,8 +21,7 @@ static pei_wrapper_entry_t load_reference_code(void)
|
|||
return prog_entry(&prog);
|
||||
}
|
||||
|
||||
struct prog prog =
|
||||
PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/refcode");
|
||||
struct prog prog = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/refcode");
|
||||
struct rmod_stage_load refcode = {
|
||||
.cbmem_id = CBMEM_ID_REFCODE,
|
||||
.prog = &prog,
|
||||
|
|
@ -41,9 +40,8 @@ static pei_wrapper_entry_t load_reference_code(void)
|
|||
|
||||
void broadwell_run_reference_code(void)
|
||||
{
|
||||
int ret, dummy;
|
||||
int dummy;
|
||||
struct pei_data pei_data;
|
||||
pei_wrapper_entry_t entry;
|
||||
|
||||
memset(&pei_data, 0, sizeof(pei_data));
|
||||
mainboard_fill_pei_data(&pei_data);
|
||||
|
|
@ -52,14 +50,14 @@ void broadwell_run_reference_code(void)
|
|||
pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0;
|
||||
pei_data.saved_data = (void *)&dummy;
|
||||
|
||||
entry = load_reference_code();
|
||||
pei_wrapper_entry_t entry = load_reference_code();
|
||||
if (entry == NULL) {
|
||||
printk(BIOS_ERR, "Reference code not found\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Call into reference code. */
|
||||
ret = entry(&pei_data);
|
||||
int ret = entry(&pei_data);
|
||||
if (ret != 0) {
|
||||
printk(BIOS_ERR, "Reference code returned %d\n", ret);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -74,20 +74,19 @@ static struct {
|
|||
|
||||
static void report_cpu_info(void)
|
||||
{
|
||||
struct cpuid_result cpuidr;
|
||||
u32 i, index, cpu_id, cpu_feature_flag;
|
||||
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
|
||||
int vt, txt, aes;
|
||||
const char *mode[] = {"NOT ", ""};
|
||||
const char *cpu_type = "Unknown";
|
||||
|
||||
index = 0x80000000;
|
||||
cpuidr = cpuid(index);
|
||||
char cpu_string[50];
|
||||
char *cpu_name = cpu_string; /* 48 bytes are reported */
|
||||
|
||||
const u32 index = 0x80000000;
|
||||
struct cpuid_result cpuidr = cpuid(index);
|
||||
if (cpuidr.eax < 0x80000004) {
|
||||
strcpy(cpu_string, "Platform info not available");
|
||||
} else {
|
||||
u32 *p = (u32 *)cpu_string;
|
||||
for (i = 2; i <= 4 ; i++) {
|
||||
for (unsigned int i = 2; i <= 4; i++) {
|
||||
cpuidr = cpuid(index + i);
|
||||
*p++ = cpuidr.eax;
|
||||
*p++ = cpuidr.ebx;
|
||||
|
|
@ -99,10 +98,10 @@ static void report_cpu_info(void)
|
|||
while (cpu_name[0] == ' ')
|
||||
cpu_name++;
|
||||
|
||||
cpu_id = cpu_get_cpuid();
|
||||
const u32 cpu_id = cpu_get_cpuid();
|
||||
|
||||
/* Look for string to match the name */
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
|
||||
for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
|
||||
if (cpu_table[i].cpuid == cpu_id) {
|
||||
cpu_type = cpu_table[i].name;
|
||||
break;
|
||||
|
|
@ -113,24 +112,23 @@ static void report_cpu_info(void)
|
|||
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
|
||||
cpu_id, cpu_type, get_current_microcode_rev());
|
||||
|
||||
cpu_feature_flag = cpu_get_feature_flags_ecx();
|
||||
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
|
||||
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
|
||||
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
|
||||
printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
|
||||
"VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
|
||||
const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
|
||||
const bool aes = (cpu_feature_flag & CPUID_AES);
|
||||
const bool txt = (cpu_feature_flag & CPUID_SMX);
|
||||
const bool vt = (cpu_feature_flag & CPUID_VMX);
|
||||
printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
|
||||
mode[aes], mode[txt], mode[vt]);
|
||||
}
|
||||
|
||||
static void report_mch_info(void)
|
||||
{
|
||||
int i;
|
||||
u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
|
||||
u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID);
|
||||
const u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
|
||||
const u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID);
|
||||
const char *mch_type = "Unknown";
|
||||
|
||||
/* Look for string to match the revision for Broadwell U/Y */
|
||||
if (mch_device == MCH_BROADWELL_ID_U_Y) {
|
||||
for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
|
||||
for (unsigned int i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
|
||||
if (mch_rev_table[i].revid == mch_revision) {
|
||||
mch_type = mch_rev_table[i].name;
|
||||
break;
|
||||
|
|
@ -144,11 +142,10 @@ static void report_mch_info(void)
|
|||
|
||||
static void report_pch_info(void)
|
||||
{
|
||||
int i;
|
||||
u16 lpcid = pch_type();
|
||||
const u16 lpcid = pch_type();
|
||||
const char *pch_type = "Unknown";
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
|
||||
for (unsigned int i = 0; i < ARRAY_SIZE(pch_table); i++) {
|
||||
if (pch_table[i].lpcid == lpcid) {
|
||||
pch_type = pch_table[i].name;
|
||||
break;
|
||||
|
|
@ -160,11 +157,10 @@ static void report_pch_info(void)
|
|||
|
||||
static void report_igd_info(void)
|
||||
{
|
||||
int i;
|
||||
u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
|
||||
const u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
|
||||
const char *igd_type = "Unknown";
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
|
||||
for (unsigned int i = 0; i < ARRAY_SIZE(igd_table); i++) {
|
||||
if (igd_table[i].igdid == igdid) {
|
||||
igd_type = igd_table[i].name;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <arch/romstage.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/intel/haswell/haswell.h>
|
||||
|
|
@ -47,8 +46,7 @@ void mainboard_romstage_entry(void)
|
|||
intel_me_status();
|
||||
|
||||
/* Save ME HSIO version */
|
||||
intel_me_hsio_version(&power_state->hsio_version,
|
||||
&power_state->hsio_checksum);
|
||||
intel_me_hsio_version(&power_state->hsio_version, &power_state->hsio_checksum);
|
||||
|
||||
perform_raminit(power_state);
|
||||
|
||||
|
|
|
|||
|
|
@ -52,10 +52,9 @@ static void print_spd_info(uint8_t spd[])
|
|||
spd_name[SPD_DDR3_PART_LEN] = 0;
|
||||
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
|
||||
|
||||
printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
|
||||
"density %d Mb\n", banks, ranks, rows, cols, capmb);
|
||||
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
|
||||
devw, busw);
|
||||
printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
|
||||
banks, ranks, rows, cols, capmb);
|
||||
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", devw, busw);
|
||||
|
||||
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
|
||||
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue