security/tcg/opal_s3: add OPAL NVMe Security Send/Receive helpers
Add the minimal NVMe admin queue and Security Send/Receive helper code used by the SMM resume unlock path. TEST=tested with rest of patch train Change-Id: Iaf4a9e23d399a093139edffc724f2b2661ca3bb1 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes
Matt DeVillier
parent
537f2acc67
commit
9a40f080ac
4 changed files with 370 additions and 0 deletions
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@ -2,5 +2,6 @@
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CPPFLAGS_common-$(CONFIG_TCG_OPAL_S3_UNLOCK) += -I$(src)/vendorcode/intel/tcg_storage_core
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smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += opal_nvme.c
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smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_core.c
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smm-$(CONFIG_TCG_OPAL_S3_UNLOCK) += ../../../vendorcode/intel/tcg_storage_core/tcg_storage_util.c
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305
src/security/tcg/opal_s3/opal_nvme.c
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305
src/security/tcg/opal_s3/opal_nvme.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "opal_nvme.h"
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#include <console/console.h>
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#include <commonlib/bsd/helpers.h>
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#include <cpu/x86/smm.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <string.h>
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#include <timer.h>
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#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
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#define NVME_ADMIN_SECURITY_RECV_CMD 0x82
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#define NVME_CC_EN (1U << 0)
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#define NVME_CC_CSS_NVM (0U << 4)
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#define NVME_CC_MPS_4K (0U << 7)
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#define NVME_CC_AMS_RR (0U << 11)
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#define NVME_CC_SHN_NONE (0U << 14)
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#define NVME_CC_IOSQES_64B (6U << 16)
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#define NVME_CC_IOCQES_16B (4U << 20)
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#define NVME_QUEUE_SIZE 2
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#define NVME_PAGE_SIZE 4096U
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#define NVME_SCRATCH_PAGES 3U
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#define NVME_SCRATCH_MIN_BYTES (NVME_SCRATCH_PAGES * NVME_PAGE_SIZE)
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#define NVME_REGS_MIN_SIZE 0x2000U
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struct nvme_sq_entry {
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u32 dw[16];
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};
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struct nvme_cq_entry {
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u32 dw[4];
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};
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/* Use the public definition from opal_nvme.h. */
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static int nvme_wait_ready(u8 *regs, bool ready)
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{
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const u64 cap = read64(regs + 0x0);
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const int timeout_units = (cap >> 24) & 0xff;
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int timeout_ms = MAX(timeout_units, 1) * 500;
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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while (!stopwatch_expired(&sw)) {
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const u32 csts = read32(regs + 0x1c);
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const bool rdy = !!(csts & 0x1);
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const bool cfs = !!(csts & 0x2);
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if (cfs)
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return -1;
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if (rdy == ready)
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return 0;
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mdelay(10);
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}
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return -1;
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}
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static int nvme_read_bar0(pci_devfn_t dev, u64 *bar_out)
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{
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const u32 bar_low = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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const bool is_mem = ((bar_low & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY);
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const bool is_64 = ((bar_low & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
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PCI_BASE_ADDRESS_MEM_LIMIT_64);
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u64 bar;
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/*
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* Callers must ensure memory decoding is enabled before attempting to
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* access the BAR.
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*/
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if (!(pci_read_config16(dev, PCI_COMMAND) & PCI_COMMAND_MEMORY))
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return -1;
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if (bar_low == 0xffffffff)
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return -1;
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if (!is_mem)
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return -1;
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bar = bar_low & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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if (is_64) {
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const u32 bar_high = pci_read_config32(dev, PCI_BASE_ADDRESS_0 + 4);
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bar |= ((u64)bar_high) << 32;
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if (!ENV_X86_64 && bar_high)
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return -1;
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}
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if (!bar)
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return -1;
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if (bar > (u64)(uintptr_t)~0)
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return -1;
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if (smm_points_to_smram((void *)(uintptr_t)bar, NVME_REGS_MIN_SIZE))
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return -1;
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*bar_out = bar;
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return 0;
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}
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static int nvme_admin_cmd(struct opal_nvme *nvme, const struct nvme_sq_entry *cmd)
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{
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struct nvme_sq_entry *s = &nvme->sq[nvme->sq_tail];
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struct nvme_cq_entry *c = &nvme->cq[nvme->cq_head];
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struct stopwatch sw;
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bool timed_out = false;
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memcpy(s, cmd, sizeof(*cmd));
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nvme->sq_tail = (nvme->sq_tail + 1) & (NVME_QUEUE_SIZE - 1);
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write32(nvme->sq_db, nvme->sq_tail);
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/* Wait for phase toggle indicating a new completion entry. */
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stopwatch_init_msecs_expire(&sw, 1000);
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while ((((read32(&c->dw[3]) >> 16) & 0x1) == nvme->cq_phase)) {
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if (stopwatch_expired(&sw)) {
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timed_out = true;
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break;
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}
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mdelay(1);
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}
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if (timed_out) {
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printk(BIOS_ERR, "OPAL NVMe: admin cmd timeout\n");
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return -1;
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}
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nvme->cq_head = (nvme->cq_head + 1) & (NVME_QUEUE_SIZE - 1);
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write32(nvme->cq_db, nvme->cq_head);
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if (nvme->cq_head == 0)
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nvme->cq_phase ^= 1;
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/* DW3 bits 31:17 are Status Field (SC + SCT + etc). */
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return (int)(c->dw[3] >> 17);
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}
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int opal_nvme_init(struct opal_nvme *nvme, pci_devfn_t dev, void *scratch, size_t scratch_size)
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{
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u64 regs;
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u16 pmcap;
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u8 *p = scratch;
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u32 cc;
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u32 csts;
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memset(nvme, 0, sizeof(*nvme));
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nvme->dev = dev;
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if (pci_read_config16(dev, PCI_VENDOR_ID) == 0xffff)
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return -1;
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if (scratch_size < NVME_SCRATCH_MIN_BYTES)
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return -1;
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p = (u8 *)ALIGN_UP((uintptr_t)p, NVME_PAGE_SIZE);
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if ((uintptr_t)p + NVME_SCRATCH_MIN_BYTES > (uintptr_t)scratch + scratch_size)
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return -1;
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nvme->sq = (struct nvme_sq_entry *)p;
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p += NVME_PAGE_SIZE;
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nvme->cq = (struct nvme_cq_entry *)p;
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p += NVME_PAGE_SIZE;
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/* Bring device to D0 if it supports PM capability. */
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pmcap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
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if (pmcap) {
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u16 pmcsr = pci_read_config16(dev, pmcap + PCI_PM_CTRL);
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if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_PM_CTRL_POWER_STATE_D0) {
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pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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pci_write_config16(dev, pmcap + PCI_PM_CTRL, pmcsr);
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udelay(1000);
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}
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}
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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if (nvme_read_bar0(dev, ®s)) {
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printk(BIOS_ERR, "OPAL NVMe: invalid BAR0\n");
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pci_and_config16(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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return -1;
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}
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nvme->regs = (u8 *)(uintptr_t)regs;
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nvme->cap = read64(nvme->regs + 0x0);
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nvme->dstrd_bytes = 4U << ((nvme->cap >> 32) & 0xf);
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nvme->sq_db = (u32 *)(nvme->regs + 0x1000 + (0 * nvme->dstrd_bytes));
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nvme->cq_db = (u32 *)(nvme->regs + 0x1000 + (1 * nvme->dstrd_bytes));
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/*
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* If controller is already running, avoid disturbing it when it is
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* already configured for our private scratch queues and appears idle.
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* Otherwise, reinitialize to private queues to avoid interacting with
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* OS-owned admin queues.
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*/
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cc = read32(nvme->regs + 0x14);
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csts = read32(nvme->regs + 0x1c);
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if ((cc & NVME_CC_EN) && (csts & 0x1)) {
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const u64 asq = read64(nvme->regs + 0x28);
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const u64 acq = read64(nvme->regs + 0x30);
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const u32 aqa = read32(nvme->regs + 0x24);
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const u32 expected_aqa = ((NVME_QUEUE_SIZE - 1) << 16) | (NVME_QUEUE_SIZE - 1);
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const u32 sq_tail = read32(nvme->sq_db) & 0xffff;
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const u32 cq_head = read32(nvme->cq_db) & 0xffff;
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if (asq == (u64)(uintptr_t)nvme->sq && acq == (u64)(uintptr_t)nvme->cq &&
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aqa == expected_aqa && sq_tail == 0 && cq_head == 0) {
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nvme->sq_tail = 0;
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nvme->cq_head = 0;
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nvme->cq_phase = (read32(&nvme->cq[0].dw[3]) >> 16) & 0x1;
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return 0;
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}
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printk(BIOS_DEBUG, "OPAL NVMe: controller running, reinitializing\n");
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}
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/* Disable controller and wait for RDY=0. */
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write32(nvme->regs + 0x14, 0);
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if (nvme_wait_ready(nvme->regs, false)) {
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printk(BIOS_ERR, "OPAL NVMe: failed to disable controller\n");
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return -1;
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}
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/* Now that the controller is disabled, it is safe to clear our queues. */
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memset(nvme->sq, 0, NVME_PAGE_SIZE);
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memset(nvme->cq, 0, NVME_PAGE_SIZE);
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/* Admin queue attributes: (CQ size-1)<<16 | (SQ size-1). */
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write32(nvme->regs + 0x24, ((NVME_QUEUE_SIZE - 1) << 16) | (NVME_QUEUE_SIZE - 1));
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write64(nvme->regs + 0x28, (u64)(uintptr_t)nvme->sq);
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write64(nvme->regs + 0x30, (u64)(uintptr_t)nvme->cq);
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/* Enable controller. */
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write32(nvme->regs + 0x14, NVME_CC_EN | NVME_CC_CSS_NVM | NVME_CC_MPS_4K |
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NVME_CC_AMS_RR | NVME_CC_SHN_NONE |
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NVME_CC_IOSQES_64B | NVME_CC_IOCQES_16B);
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if (nvme_wait_ready(nvme->regs, true)) {
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printk(BIOS_ERR, "OPAL NVMe: controller not ready\n");
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return -1;
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}
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nvme->sq_tail = 0;
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nvme->cq_head = 0;
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nvme->cq_phase = 0;
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return 0;
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}
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void opal_nvme_deinit(struct opal_nvme *nvme)
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{
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/* Keep controller state as-is; OS will reinitialize if needed. */
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(void)nvme;
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}
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static int nvme_security_cmd(struct opal_nvme *nvme, u8 opcode, u8 protocol, u16 sp_specific,
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const void *buf, size_t buf_size)
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{
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struct nvme_sq_entry cmd = { 0 };
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const u64 prp1 = (u64)(uintptr_t)buf;
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cmd.dw[0] = opcode; /* CID is left as 0 */
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cmd.dw[1] = 0; /* NSID = 0 (controller) */
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cmd.dw[6] = (u32)prp1;
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cmd.dw[7] = (u32)(prp1 >> 32);
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/*
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* NVMe command dwords are little-endian on x86. The Security Protocol
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* Specific field is a numeric value in the command; do not byte-swap it.
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*/
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cmd.dw[10] = ((u32)protocol << 24) | ((u32)sp_specific << 8);
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cmd.dw[11] = (u32)buf_size;
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return nvme_admin_cmd(nvme, &cmd);
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}
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int opal_nvme_security_send(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
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const void *buf, size_t buf_size)
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{
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return nvme_security_cmd(nvme, NVME_ADMIN_SECURITY_SEND_CMD, protocol, sp_specific,
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buf, buf_size);
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}
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int opal_nvme_security_recv(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
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void *buf, size_t buf_size, size_t *xfer_out)
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{
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int ret;
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if (xfer_out)
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*xfer_out = 0;
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ret = nvme_security_cmd(nvme, NVME_ADMIN_SECURITY_RECV_CMD, protocol, sp_specific,
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buf, buf_size);
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if (ret)
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return ret;
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if (xfer_out)
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*xfer_out = buf_size;
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return 0;
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}
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41
src/security/tcg/opal_s3/opal_nvme.h
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41
src/security/tcg/opal_s3/opal_nvme.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SECURITY_TCG_OPAL_S3_OPAL_NVME_H
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#define SECURITY_TCG_OPAL_S3_OPAL_NVME_H
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#include <device/pci_type.h>
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#include <types.h>
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struct nvme_sq_entry;
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struct nvme_cq_entry;
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struct opal_nvme {
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pci_devfn_t dev;
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u8 *regs;
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u64 cap;
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u32 dstrd_bytes;
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struct nvme_sq_entry *sq;
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struct nvme_cq_entry *cq;
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u32 *sq_db;
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u32 *cq_db;
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u16 sq_tail;
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u16 cq_head;
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u8 cq_phase;
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};
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/*
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* Initialize a minimal NVMe admin queue in the provided scratch buffer.
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*
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* The scratch memory must not be in SMRAM. It must be preserved across S3.
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*/
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int opal_nvme_init(struct opal_nvme *nvme, pci_devfn_t dev, void *scratch, size_t scratch_size);
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void opal_nvme_deinit(struct opal_nvme *nvme);
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int opal_nvme_security_send(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
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const void *buf, size_t buf_size);
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int opal_nvme_security_recv(struct opal_nvme *nvme, u8 protocol, u16 sp_specific,
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void *buf, size_t buf_size, size_t *xfer_out);
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#endif
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23
src/security/tcg/opal_s3/opal_secure.h
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23
src/security/tcg/opal_s3/opal_secure.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SECURITY_TCG_OPAL_S3_OPAL_SECURE_H
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#define SECURITY_TCG_OPAL_S3_OPAL_SECURE_H
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#include <stddef.h>
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#include <types.h>
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static inline void opal_explicit_bzero(void *ptr, size_t len)
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{
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volatile u8 *p = (volatile u8 *)ptr;
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if (!ptr || !len)
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return;
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while (len--)
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*p++ = 0;
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/* Prevent the compiler from optimizing the stores away. */
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__asm__ __volatile__("" : : "r"(ptr) : "memory");
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}
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#endif
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