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vc/amd/opensil/phoenix_poc: Adjust headers from Genoa to Phoenix

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As directory was copied from genoa_poc, we need to adjust headers to
correspond to phoenix_poc repository.

Change-Id: Id3aeaf6ecf138ea94282ae2a308a45c77ff73b02
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91481
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Alicja Michalska 2026-03-01 02:48:49 +01:00 • committed by Matt DeVillier
commit 513899c3c8
5 changed files with 7 additions and 11 deletions
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2
src/vendorcode/amd/opensil/phoenix_poc/acpi.c
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@ -4,7 +4,7 @@
#include <Sil-api.h>
#include <SilCommon.h>
#include <xSIM-api.h>
#include <FCH/Common/FchCommonCfg.h>
#include <FCH/Common/FchCommon.h>
#include "../opensil.h"

3
src/vendorcode/amd/opensil/phoenix_poc/memmap.c
View file

@ -2,7 +2,7 @@
#include <SilCommon.h>
#include <Sil-api.h> // needed above ApobCmn.h
#include <ApobCmn.h>
#include <APOB/Common/ApobCmn.h>
#include <xPRF-api.h>
#include "../opensil.h"
@ -32,7 +32,6 @@ const char *opensil_get_hole_info_type(uint32_t type)
{ReservedCxl, "ReservedCxl"},
{ReservedCxlAlignment, "ReservedCxlAlignment"},
{ReservedCpuTmr, "ReservedCpuTmr"},
{ReservedRasEinj, "ReservedRasEinj"},
{MaxMemoryHoleTypes, "MaxMemoryHoleTypes"},
};

4
src/vendorcode/amd/opensil/phoenix_poc/mpio/chip.c
View file

@ -4,8 +4,8 @@
#include <device/pci_def.h>
#include <Mpio/Common/MpioStructs.h>
#include <Mpio/MpioClass-api.h>
#include <NBIO/NbioClass-api.h>
#include <RcMgr/DfX/RcManager4-api.h>
#include <Nbio/NbioClass-api.h>
#include <RcMgr/DfX/RcManager-api.h>
#include <vendorcode/amd/opensil/opensil.h>
#include <xSIM-api.h>

2
src/vendorcode/amd/opensil/phoenix_poc/opensil_config.template
View file

@ -1,5 +1,3 @@
CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE##
CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE##
CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE##
CONFIG_PLAT_NUMBER_SOCKETS=1
CONFIG_SOC_F19M10=y

7
src/vendorcode/amd/opensil/phoenix_poc/ramstage.c
View file

@ -1,14 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <FCH/Common/FchCommonCfg.h>
#include <FCH/Common/FchCore/FchSata/FchSata.h>
#include <RcMgr/DfX/RcManager4-api.h>
#include <FCH/Common/FchCommon.h>
#include <RcMgr/DfX/RcManager-api.h>
#include <amdblocks/reset.h>
#include <bootstate.h>
#include <cbmem.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <soc/soc_chip.h>
#include <soc/amd/phoenix/chip.h>
#include <static.h>
#include <stdio.h>
#include <xSIM-api.h>