nb/intel/haswell: Move PEG device macros to header

These can and will be used in other files in subsequent commits.

Change-Id: Iba0515151252b22f0211e8ab1470c70dfd172929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Angel Pons 2026-03-09 19:02:45 +01:00 committed by Matt DeVillier
commit 76290e8cdc
3 changed files with 7 additions and 6 deletions

View file

@ -8,7 +8,7 @@
#include "haswell.h"
static bool peg_hidden[3];
static bool peg_hidden[MAX_PEG_FUNC];
static void haswell_setup_bars(void)
{
@ -111,7 +111,7 @@ void haswell_unhide_peg(void)
{
u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
for (u8 fn = 0; fn <= 2; fn++) {
for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
if (peg_hidden[fn]) {
deven |= DEVEN_D1F0EN >> fn;
peg_hidden[fn] = false;

View file

@ -7,10 +7,6 @@
#include <northbridge/intel/haswell/vcu_mailbox.h>
#include <types.h>
#define PEG_DEV(func) PCI_DEV(0, 1, func)
#define MAX_PEG_FUNC 3
static void peg_dmi_unset_and_set_mask_pcicfg(
volatile union pci_bank *const bank,
const uint32_t offset,

View file

@ -16,6 +16,11 @@
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
/* Device 0:1.x PCI configuration space (PCI Express Graphics) */
#define PEG_DEV(func) PCI_DEV(0, 1, func)
#define MAX_PEG_FUNC 3
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */