non-cacheable
Add support to split the dram_aop memory region into three in order to
map dram_aop_cmd_db as non-cacheable. The purpose of dram_aop_config
is memory region where the aop_devcfg.mbn image is loaded.
Test=1. Build and boot on X1P42100.
2. Dump the MMU table in coreboot ramstage and verify whether the region
is mapped as non-cacheable.
Change-Id: Id73d878b7d343f248a845bd5727c43e22c4c348a
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90521
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF| AM:0000000081C60000--0000000081C7FFFF| s | | 00001000| read/write access exec | yes| inn| non-cacheable | 1| no | \\ramstage\Global\_dram_aop_cmd_db'
Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.
The following regions are added to the SSRAM section:
- qsee: 100K at 0x14680000
- qdss_usb_trace: 8K at 0x146A6000
- aop_imem: 8K at 0x146A8000
The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.
BUG=b:456953373
TEST=Able to build and boot google/quenbih.
Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.
Details:
- The previous location of the PRERAM_STACK starting at 0x14680000 in
SSRAM is now reserved for QC QSEE.
- This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
the available memory region starting at 0x14850000 in the BSRAM.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.
Changes
- Pre-RAM Stack: The temporary stack used before DRAM is ready is
defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
replacing the old generic STACK definition.
- Post-RAM Stack: The final stack is defined using
POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.
- The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
accommodate the new 16KB post-RAM stack, avoiding memory overlap.
This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
w/o this patch
```
[SPEW ] stack: top_of_stack address is 0x14684000
```
w/ this patch
```
[SPEW ] stack: top_of_stack address is 0x80004000
```
Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the X1P42100 SoC, the System Debug Image (SDI) flow is handled by
the Always-On Processor (AOP), unlike previous architectures (e.g.,
Kodiak) which utilized a dedicated 'QcSDI' image.
Rename the memory region at 0x14699000 from 'qcsdi' to 'aop_sdi' to
accurately reflect ownership by the AOP and to align with the new
chipset architecture. This change clarifies the memory map and serves
as a prerequisite for removing legacy QcSDI artifacts once the
modern SDI flow is fully enabled.
BUG=b:456953373
TEST=Build and boot on google/quenbih target.
Change-Id: Ic5626c06decaadfd459aa21bde4efcfec92e1e47
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90505
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.
TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.
Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
clock enablement
Add register address and clock value definitions required to enable
the display clock. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Generated image.serial.bin and verified boot on X1P42100.
Validated only basic device boot functionality, as clock enablement API
and its invocation sequence from display driver are not yet implemented.
Change-Id: Id23dd12c9c1ee4968546c8b928f9360163446a9d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ramdump is a debug image loaded during a crash to capture memory
contents for post-crash analysis. This patch adds support for
loading this image during the qclib_rerun() sequence.
Key changes:
1) Introduce QC_RAMDUMP_ENABLE Kconfig option to control ramdump image
loading.
2) Add qclib_check_dload_mode() as a weak function that works in
conjunction with the Kconfig check to decide whether the ramdump
image should be loaded.
3) Add new CBFS file entry and table entry definition for ramdump_meta.
4) Re-use "apdp_ramdump_meta" region for ramdump metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I42bcd74c3d236a6af49ec4b548bc9cda33bd0825
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90306
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds build rules for packing the APDP image in CBFS.
It also updates the memory layout to include a dedicated region
for APDP metadata storage (4KB at 0x14890000).
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: Ia3093ef6619dd504c829cf6ba6f672f16070f68a
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces a new Kconfig option, QC_APDP_ENABLE, to control
Application Processor Debug Policy (APDP) image loading. When this
option is enabled, the APDP image is loaded during the
qclib_load_and_run() sequence. It also adds a new CBFS file entry and
table entry definition for apdp_meta, along with a memory region symbol
apdp_ramdump_meta for metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I8d0847c99a1129359f2c758b7a07b9c022f1c8c8
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90303
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to reserve 33 MB DRAM memory for display in memlayout.ld
file.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Basic device boot functionality with the specified memory reservation
has been validated. Display functionality has not yet been tested, as
the display driver porting is yet to be done.
Change-Id: I49a4a20b9869bc5cf0b11f4eb6cff7865bb2e761
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Power-On (PON) history log parsing and status API to the
SOC layer (soc/qualcomm/x1p42100/pmic.c).
This code is specific to the Qualcomm PMIC architecture (reading
registers for PON events and reasons), making it an SOC-specific
utility rather than a board-level policy. Moving it here improves
modularization and allows other X1p42100-based boards to reuse this
critical power management logic.
Key APIs introduced:
- pm_pon_read_pon_hist(): Reads the raw circular PON event log
from the PMIC, reverses the buffer to put the latest entry first.
- is_pon_on_ac(): Interprets the log to detect if the power-on
reason was due to AC/Cable Power (PON_CBLPWR_RSN).
Key changes:
- Create src/soc/qualcomm/x1p42100/include/soc/pmic.h with PON
definitions and API prototypes.
- Create src/soc/qualcomm/x1p42100/pmic.c containing the PON
log reading and parsing logic.
- Add pmic.c to the SOC's romstage build via Makefile.mk.
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I8cd1478b9f8d53519f603e8f5168d0a51fa54971
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90192
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API, spmi_read_bytes(), to allow reading a
sequence of registers from a Qualcomm PMIC using the SPMI bus.
While the existing spmi_read8() is suitable for single-byte
access, reading large log areas (like the PON history log)
requires iterating over a contiguous block of addresses. This
new function encapsulates the required loop, calling spmi_read8()
sequentially for each address in the range.
This abstraction improves code cleanliness and makes high-level PMIC
log parsing much simpler.
Key changes:
- Define spmi_read_bytes() prototype in qcom_spmi.h.
- Implement spmi_read_bytes() in spmi.c to perform sequential
reads using spmi_read8().
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I6017336a882a8fa8d771b0127e78dd4f0fdbdd0e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the SPMI_ADDR macro to wrap both the slave and reg
arguments in parentheses.
The previous definition, ((slave << 16) | reg), led to incorrect
address calculation when the slave argument was an arithmetic or
logical expression (e.g., (a | b)), as the bit-shift operator (<<)
has higher precedence than the logical OR (|).
The revised macro guarantees that the full slave expression is
evaluated before the bit shift, ensuring correct SPMI register
address construction.
Key changes:
- Wrap slave and reg arguments in parentheses within
SPMI_ADDR definition.
BUG=b:439819922
TEST=Verify that the SPMI_ADDR output is correct.
e.g. SPMI_ADDR(0x02 | 0x01, 0x200)
Output before this change:
```
((0x02 | 0x01 << 16) | 0x200)
(0x02 | 0x010000 | 0x200)
(0x010202)
```
Output after this change:
```
(((0x02 | 0x01) << 16) | 0x200)
(((0x03) << 16) | 0x200)
((0x030000) | 0x200)
(0x030200)
```
Change-Id: I58b36b62f0b5a59c03a1c1d08640fe9086d81d7a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to configure DFSR table, introduce qupv3_clock_v2
structure to calculate register addresses for serial engines 2
and 3. Update CBCR registers to use the new structure for QUPv3
clock enablement.
BUG=b:444617760
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Dump DFSR registers for corresponding QUP and check if values are
updated properly into correct register address.
Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit updates the linker script to properly define and name the
DMA coherent memory regions used before and after DRAM initialization.
1. Rename Pre-RAM DMA Region:
The existing `DMA_COHERENT` region allocated in BSRAM at `0x14857000` is
renamed to `PRERAM_DMA_COHERENT`. This aligns the linker script with the
code changes (in `mmu.c`) which use the more specific name for the early
boot DMA buffer.
2. Add Post-RAM DMA Region:
A new region, `POSTRAM_DMA_COHERENT`, is defined at the very start of
DRAM (`0x80000000`) with an 8KB size. This region is intended for
general-purpose DMA operations that occur after DRAM is active,
ensuring a reserved, known, and uncached region for peripherals.
The memory map diagram comments are also updated to reflect these new
region names.
BUG=b:456953373
TEST=Able to build and boot google/quenbi.
Change-Id: I6fb4b9bf3425b311169ac43e1997f6574b571e00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90098
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit relocates the following two regions:
1. `ddr_information`
2. `WATCHDOG_TOMBSTONE`
Previously, these regions were allocated in a higher address range
(starting near 0x14800000).
The regions are now defined within SSRAM`:
- `ddr_information` is moved from `0x14860000` to `0x146ABFE8`.
- `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`.
This memory map change updates the linker script's visual diagram and
section definitions to reflect the new memory layout.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: I4545722a836ec472e8086d1a941515cb3956c763
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.
Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.
The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.
This is necessary for DMA operations that occur after DRAM is
initialized.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch relocates the coreboot stack from the BSRAM (Boot IMEM)
region to the SSRAM (Shared System RAM) region.
The 16K stack definition is moved from:
BSRAM region (0x14850000)
To:
SSRAM region (0x14680000)
This move is crucial because the BSRAM region is actively cleared during
the later stages of the IP loading process, which would wipe the stack
and lead to instability. Placing the stack in the persistent SSRAM
ensures it remains accessible throughout the early boot process.
BUG=BUG=b:456953373
TEST=Able to build google/quenbi w/ new stack region.
Change-Id: I59cd14fed2a5907bcbb8bed027dd5a55eb73e56d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90137
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Instrument the Qualcomm QCLib flow with timestamps to measure
execution time for both the initial loading/running phase and the
subsequent re-entry phase.
The timestamps are placed as follows:
- TS_QUALCOMM_QCLIB_INIT_START/END: Tracks the execution of
`qclib_load_and_run()`.
- TS_QUALCOMM_QCLIB_REINIT_START/END: Tracks the execution of
`qclib_rerun()`, which typically handles the AOP bring-up.
This instrumentation helps in profiling and optimizing the boot
performance on Qualcomm platforms.
Change-Id: I200ea5a78f4630000e80aed6dc38581af4d2e8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90112
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The firmware binaries for UART, SPI, I2C, and GSI are loaded early in
the boot process. Disable CBFS compression for these files by explicitly
setting $(CBFS_..._compression) to 'none'.
This ensures the firmware is stored and loaded as a raw binary,
mitigating potential boot time impact with decompression.
BUG=b:449871690
TEST=Able to save ~10ms of the boot time while booting google/quenbi.
Change-Id: I0418aadeb860143e766b0fe1ba10a0316d4cc6a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor Kconfig dependency by moving the selection of Secure OS
(TrustZone/TEE) features from the mainboard configuration to the
specific SoC configuration layer.
The selections for `ARM64_USE_SECURE_OS` and
`ARM64_USE_SECURE_OS_PAYLOAD` are moved from `BOARD_GOOGLE_BLUEY_COMMON`
to `SOC_QUALCOMM_HAMOA`.
This ensures that the Secure OS requirements are correctly associated
with the Hamoa chipset family itself, leading to better modularity and
future compatibility for Hamoa-based platforms.
Crucially, this change allows for precise control of the Secure OS
(BL32 firmware) applicability. By selecting the feature only within
`SOC_QUALCOMM_HAMOA`, we can ensure that platforms utilizing the
"Purwa SoC" family (which currently does not have a ready/available
SecureOS) automatically avoid the selection of these Kconfig options.
The change is verified by ensuring the QTEE (SecureOS) feature is
disabled for platforms using the Purwa SoC, specifically verified on the
google/quenbi mainboard.
BUG=b:459268465
TEST=Ensure disabling QTEE aka SecureOS feature for google/quenbi w/
Purwa SoC.
AP firmware log shows the expected path taken when SecureOS is disabled:
```
WARNING: No QTEE entry point provided by BL2 boot loader,
Booting device without QTEE initialization.
```
Change-Id: Ic82a29a4330cc6e5f99727fc40ec73b38cbbc72d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90011
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for configuring the NVMe Power Loss Notification (PLN)
GPIO before powering on the NVMe device.
The Hamoa target has the PLN signal wired to SoC GPIO 157. The voltage
level conversion circuitry between the SoC (1.2V) and NVMe (3.3V) causes
the PLN signal voltage level to vary depending on the NVMe part used.
This change configures GPIO 157 as an input with no pull resistors and
2mA drive strength to ensure proper PLN signal handling and allow the
GPIO to be used for other hardware configurations.
Changes:
- Add NVME_PLN_GPIO definition for GPIO(157)
- Add nvme_core_pln_gpio() function to configure PLN GPIO
- Update gcom_pcie_power_on_ep() to call nvme_core_pln_gpio() before
enabling NVMe power regulator
TEST=Boot the Google/Bluey board and verify NVMe device is detected
and functional
Debug logs:
Initializing NVMe controller 1e0f:000c
nvme_ctrlr_init: PCI Command register = 0x2
nvme_ctrlr_init: PCI Status register = 0x10
nvme_ctrlr_init: PCI Command after bus master enable = 0x6
iosq_sz = 11, iocq_sz = 11
nvme_wait_status: Waiting for CSTS & 0x1 == 0x0, timeout=30000 ms
nvme_ctrlr_init: Waited 100ms after controller disable
nvme_enable_controller: CSTS before enable = 0x0
nvme_enable_controller: CAP register = 0x303c03ffff
nvme_enable_controller: CAP.TO timeout = 30000 ms
nvme_enable_controller: Writing CC register = 0x460001
nvme_enable_controller: CC register readback = 0x460001
nvme_wait_status: Waiting for CSTS & 0x1 == 0x1, timeout=30000 ms
nvme_enable_controller: CSTS after enable = 0x1 (status=0)
Identified NVMe model KBG50ZNS256G KIOXIA
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
Change-Id: Icc22cfd397a0adbc051b2b1a2178aeedb7389ac0
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90037
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.
Avoid OTG enablement polling when in sink mode
BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.
Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.
Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
exceeded actual requirements, as OTG enablement consistently
completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
operated in sink mode, where OTG functionality is irrelevant since
the port receives rather than provides power
Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
20ms, maintaining adequate margin (>40% headroom) while reducing boot
time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
status polling entirely for sink-mode ports, as demonstrated by the
"Primary in SNK mode - skipping OTG status read" log entry
The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.
Debug logs:
[DEBUG] QMP PHY SS0 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Primary VBUS SuperSpeed
[INFO ] Primary in SNK mode - skipping OTG status read
[INFO ] Primary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x1a
[INFO ] Src Status (0x2B08): 0x00
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0x02
[DEBUG] USB HS PHY initialized for index 3
[DEBUG] QMP-1x16 USB4 DP PHY SS1 init
[DEBUG] QMP PHY SS1 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Secondary VBUS SuperSpeed
[INFO ] Secondary in SRC mode - OTG Status: 0x02, State: 0x02
(OTG Enabled) - Time: 14 ms
[INFO ] Secondary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x4b
[INFO ] Src Status (0x2B08): 0x08
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0xa6
confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.
Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.
The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.
BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.
Without this CL -
USB2 key doesn't work for C1.
Verified HS1 functionality by turning on L14B from coreboot.
Before USB insertion:
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Added USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Removed USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The
carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is
the DRAM size. This region is protected by QTEE and must remain
reserved to prevent access by other components.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified carveout region reservation via depthcharge serial log.
Prior to reservation, the memory wipeout range was [0x000000f61f7920,
0x000000ff800000). After reserving the carveout, the range is reduced
to [0x000000f61f7920, 0x000000f7c00000).
```
Wipe memory regions:
[0x00000080000000, 0x00000080a00000)
[0x000000815a0000, 0x00000081a00000)
[0x00000081cf4000, 0x00000081e00000)
[0x00000082800000, 0x00000085380000)
[0x00000085f80000, 0x000000866c0000)
[0x00000091380000, 0x000000c72c4000)
[0x000000c7800000, 0x000000d8000000)
[0x000000d9600000, 0x000000f1000000)
[0x000000f61f7920, 0x000000f7c00000)
[0x00000880000000, 0x00000c00000000)
```
Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces necessary changes to correctly initialize the
Qualcomm X1p42100 USB4/DP PHY based on the USB Type-C CC polarity
detection.
When a Type-C cable is connected, the CC lines determine the
connector orientation (polarity). The USB PHY lanes must be swapped
accordingly to ensure the SuperSpeed signals are routed correctly.
Key changes:
- Adds 'get_usb_typec_polarity()' to read the CC polarity state from
the PMIC (SMB1/SMB2) via the 'SCHG_TYPE_C_MISC_STATUS' register.
- Extends 'qmp_usb4_dp_phy_ss_init()' to accept a 'polarity_inverse'
boolean.
- Uses the polarity state to set the 'SW_PORTSELECT' register in the
USB4/DP common configuration, effectively swapping the lanes when
needed.
- Calls the updated PHY initialization function with the appropriate
polarity for both primary (SS0) and secondary (SS1) USB instances.
This ensures robust USB functionality regardless of the cable insertion
orientation.
BUG=b:448107633
TEST=Verify USB-C works in both polarities on Google/Quenbi.
Without this CL -
USB3 key doesn't work in inverted polarity.
With this CL -
USB3 key works in both polarities.
Change-Id: I1855a12e32a76032d4c1b57770143c152b806008
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enable clocks for Type-C ports C0 and C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
BUG=b:448107633
TEST = Verified that all the clocks added are ON during usb init.
BIT31[CLK OFF] of CBCR register of respective clock indicates
clock status.
Clock Configuration Status:
Clock Name State Register Value
----------------------------------------------------------------
gcc_usb30_mp_master_clk ON 0x00117018 0x00000001
gcc_usb30_mp_sleep_clk ON 0x00117024 0x00000001
gcc_usb30_mp_mock_utmi_clk ON 0x00117028 0x00000001
gcc_usb3_mp_phy_aux_clk ON 0x00117288 0x00000001
gcc_usb3_mp_phy_com_aux_clk ON 0x0011728C 0x00000001
gcc_usb3_mp_phy_pipe_0_clk ON 0x00117290 0x00000001
gcc_usb3_mp_phy_pipe_1_clk ON 0x00117298 0x00000001
gcc_cfg_noc_usb3_mp_axi_clk ON 0x001173CC 0x00000001
gcc_aggre_usb3_mp_axi_clk ON 0x001173D0 0x00000001
gcc_sys_noc_usb_axi_clk ON 0x0012D014 0x00000001
gcc_cfg_noc_usb_anoc_north_ahb_clk ON 0x0012D028 0x00000000
gcc_cfg_noc_usb_anoc_south_ahb_clk ON 0x0012D02C 0x00000000
gcc_aggre_usb_noc_axi_clk ON 0x0012D034 0x00000001
gcc_cfg_noc_usb_anoc_ahb_clk ON 0x0012D024 0x00000000
gcc_usb30_prim_master_clk ON 0x00139018 0x00000001
gcc_usb30_prim_sleep_clk ON 0x00139024 0x00000001
gcc_usb30_prim_mock_utmi_clk ON 0x00139028 0x00000001
gcc_usb3_prim_phy_com_aux_clk ON 0x00139064 0x00000001
gcc_usb3_prim_phy_pipe_clk ON 0x00139068 0x00000001
gcc_cfg_noc_usb3_prim_axi_clk ON 0x0013908C 0x00000001
gcc_aggre_usb3_prim_axi_clk ON 0x00139090 0x00000001
gcc_cfg_noc_usb3_sec_axi_clk ON 0x001A108C 0x00000001
gcc_aggre_usb3_sec_axi_clk ON 0x001A1090 0x00000001
gcc_usb30_sec_master_clk ON 0x001A1018 0x00000001
gcc_usb30_sec_sleep_clk ON 0x001A1024 0x00000001
gcc_usb30_sec_mock_utmi_clk ON 0x001A1028 0x00000001
gcc_usb3_sec_phy_aux_clk ON 0x001A1060 0x00000001
gcc_usb3_sec_phy_com_aux_clk ON 0x001A1064 0x00000001
gcc_usb3_sec_phy_pipe_clk ON 0x001A1068 0x00000001
Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.
Changes include:
- Declaring new memory regions in symbols_common.h.
- Defining base addresses and sizes for these regions in memlayout.ld.
- Marking these regions as reserved in soc_read_resources() to
prevent overwrites by coreboot.
- Modifying CBMEM top address.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).
The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.
The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.
w/o this patch
```
[ERROR] Unable to load previous training data.
```
w/ this patch
```
[WARN ] qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```
Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select the newly introduced `HAVE_CBFS_FILE_OPTION_BACKEND` capability
for the Qualcomm x1p42100 SoC family.
This SoC is used in ChromeOS devices that rely on the CBFS file backend
to store and retrieve runtime configuration options (like the QCLib
configuration data). Selecting this capability ensures the correct
option backend is chosen in the Kconfig `Option backend to use` choice.
TEST=Build and boot a board using the x1p42100 SoC (e.g., bluey).
Confirm the `CONFIG_USE_CBFS_FILE_OPTION_BACKEND` option is enabled
in the build.
Change-Id: Ie0dee155a504da215669a79d7100cdbaf97d5261
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce a new static function, `qclib_debug_log_level`, that
checks a runtime-configurable option, "qclib_debug_level", to
control whether QCLib enables serial logging.
This allows for dynamic control of QCLib's verbose output via a
coreboot option instead of relying solely on the static
`CONFIG(CONSOLE_SERIAL)` Kconfig option. This is necessary because
while the serial console might be enabled for general coreboot
logging, the user may want to suppress the often extensive and
low-level output from QCLib to keep the console clean during normal
operations.
The check for enabling QCLib's serial output is updated from
`if (CONFIG(CONSOLE_SERIAL))` to
`if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())`
The option value is read using
`get_uint_option("qclib_debug_level", 1)`, meaning the default
behavior is to enable QCLib logging if `CONSOLE_SERIAL` is set,
maintaining backward compatibility unless the option is explicitly
set to 0 at runtime.
BUG=b:445211186
TEST=Build and boot a Qualcomm platform with CONFIG_CONSOLE_SERIAL
enabled. Confirmed QCLib logs are present by default.
Set option "qclib_debug_level" to 0 via CBFS option and confirmed
QCLib logs are suppressed while coreboot serial output remains
active.
Change-Id: I2c7326fae889508f09e1eb5e3863456cf54f5c29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for HS-PHY/SS-PHY and DWC3 USB controllers
for USB Type A Host support.
TEST = Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: Ife08801062da5a8f87491b020b3828c246aadea8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for USB controller, PHY and NOC clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Verify the boot process on the X1P42100 by creating an
image.serial.bin. After booting, confirm that the USB clocks are
on by inspecting the Clock Branch Control Register (CBCR) for
each clock. The status is indicated by BIT31, where a low value
means the clock is on.
Change-Id: Ic78e75c2c9963311530172d802aabb03f540060c
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.
TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.
Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the DRAM memory reservation range for TF-A
to align with the latest Bluey memory layout specifications.
TEST=Verified boot up on google/bluey.
Change-Id: Ifb67e591d0f3d28cd6b0856198b29af49c2aab4c
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
