coreboot/src/soc/qualcomm
Hari L 2b7b89ae31 soc/qualcomm/x1p42100: Update PCIE PHY init sequence
Update PCIE PHY sequence as per hardware setting reference(HSR)
specifically, PCIE RC Config sequence(PCIE RC Cfg Seq).

Key changes:

- Add RX1-specific overrides applied after common RX settings
- Update TX lane mode register (LANE_MODE_3: 0x90 -> 0x51)
- Modify RX calibration and equalization parameters
- Adjust RX signal detection level (0xAA -> 0xCC)
- Add NVME_PLN_GPIO definition for Power Loss Notification

The changes ensure proper PHY initialization for PCIe Gen 4 link
establishment and improve signal integrity.

TEST=Boot the Google/Bluey board and check that the link is up

Debug logs:

[INFO ]  Enumerating buses...
[SPEW ]  Show all devs... Before device enumeration.
[SPEW ]  Root Device: enabled 1
[SPEW ]  CPU_CLUSTER: 0: enabled 1
[SPEW ]  DOMAIN: 00000000: enabled 1
[SPEW ]  PCI: 00:00:00.0: enabled 1
[SPEW ]  Compare with tree...
[SPEW ]  Root Device: enabled 1
[SPEW ]   CPU_CLUSTER: 0: enabled 1
[SPEW ]   DOMAIN: 00000000: enabled 1
[SPEW ]    PCI: 00:00:00.0: enabled 1
[DEBUG]  Root Device scanning...
[SPEW ]  scan_static_bus for Root Device
[DEBUG]  CPU_CLUSTER: 0 enabled
[INFO ]  Setup PCIe in RC mode
[DEBUG]  Skipping pipe
[DEBUG]  PCIe QPHY Initialized took 13us
[INFO ]  PCIe Link speed configured in Gen 4
[INFO ]  PCIe link is up
[NOTE ]  PCIe enumerated succussfully..
[DEBUG]  DOMAIN: 00000000 enabled
[DEBUG]  DOMAIN: 00000000 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG]  PCI: 00:00:00.0 subordinate bus PCI Express
[DEBUG]  PCI: 00:00:00.0 [17cb/0111] enabled
[DEBUG]  PCI: 00:00:00.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:00:00.0
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG]  PCI: 00:01:00.0 [1e0f/000c] enabled
[INFO ]  PCI: 00:00:00.0: Setting Max_Payload_Size to 256
		for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:00.0 finished in 29 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 60 msecs
[SPEW ]  scan_static_bus for Root Device done
[DEBUG]  scan_bus: bus Root Device finished in 220 msecs
[INFO ]  done

Debug logs show successful PCIe enumeration with Gen 4 link up
and device [1e0f/000c] detected.

Change-Id: Ifb07839818e30622e35b6ee39af824fd5f19dec5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2025-11-16 18:36:21 +00:00
..
common soc/qualcomm/x1p42100: Update PCIE PHY init sequence 2025-11-16 18:36:21 +00:00
ipq40xx arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
ipq806x arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
qcs405 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
sc7180 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
sc7280 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
x1p42100 soc/qualcomm/x1p42100: Update PCIE PHY init sequence 2025-11-16 18:36:21 +00:00