The mtk_ddp_ovlsys_start function is updated to take edid and path
as arguments. This allows the function to configure the framebuffer
address and overlay for DISP_PATH_DUAL_MIPI path.
BUG=b:319511268
TEST=cherry pick CB:90504 and manual enable BMP_LOGO related configs.
The logo is drawn in the ramstage.
Change-Id: I60809f7062907617f2af1badcad9f53477911020
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add an option to lock the regions BOOTBLOCK and COREBOOT, leaving the
regions TOPSWAP and COREBOOT_TS for updates in an Intel Top Swap
redundancy scenario.
This means that the user can now write and choose to boot from the
update regions, selecting the attempt_slot_b CMOS option, and there is
a protected golden copy of the entire firmware, that cannot be
overwritten and can be reverted to by resetting CMOS.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: Ia6dea22c41e2fc778af6ca7049b72c92686ec85f
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Before CPU resume, it is necessary to reinitialize the MTE-related
settings of booker in MCUPM to prevent the loss of booker
configurations after resume.
BUG=b:467186613
TEST=Build pass, Verify S/R OK on Navi and Sapphire.
Change-Id: Ieaf4c2ea0f8a5c372a5dbf4d0f6c44fbd978e6a6
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90546
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.
Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map(). This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.
The branching is done on the state of RTC BUC to always use the current
bootblock. Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.
Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
- recognize both "BOOTBLOCK" and "TOPSWAP" regions
- recognize both "COREBOOT" and "COREBOOT_TS" regions
- reset metadata cache before processing each region as cache may now
be invalid
SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.
This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.
Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a correction of CB:89570 (commit 04ea4724e2 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")). It wasn't obvious
that CBFS verification depends on bootblock being added first (otherwise
cbfstool considers CBFS verification to be disabled because anchor is
part of a bootblock). Correct this and add a comment for anyone else
who might edit this code in the future.
The issue manifested itself in build failing to perform CBFS
verification via cbfstool when the firmware was built with
CBFS_VERIFICATION enabled.
Change-Id: If775480394270fc05206cde0707c511b126265d3
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90436
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Take advantage of cbfstool's ability to operate on multiple regions and
introduce a variable with a list of main CBFS regions: it's just
"COREBOOT" in most cases, but becomes "COREBOOT,COREBOOT_TS" when Top
Swap update mechanism is enabled (see [0]).
This is meant to simplify Makefiles by avoiding extra branches in
existing and future changes.
[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: If537d0d21a2867fafc2241ea9a0b4c0c6ca290a8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90435
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is a correction of CB:89570 (commit 04ea4724e2 ("Makefile.mk:
separate bootblocks into BOOTBLOCK and TOPSWAP")) which has FITs in both
BOOTBLOCK and TOPSWAP point at microcode in COREBOOT region.
This can be tested by comparing outputs of
build/util/cbfstool/ifittool -f build/coreboot.rom -r TOPSWAP -D
and
build/util/cbfstool/ifittool -f build/coreboot.rom -r BOOTBLOCK -D
with microcode addresses as shown by
uefitool build/coreboot.rom
The addresses in two regions must not be identical and their last six
hex digits must match what uefitool shows in "Base:" field (not
"Offset:").
Change-Id: Ie37aee7a26be18d1a4d8993afd2a2484c38c0b1e
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
The addition provides a way to select USE_OPTION_TABLE for a mainboard
which depends on the CMOS backend for options. This is needed to
support update mechanism based on Top Swap that permits recovery via a
CMOS reset (see [0]). The indirection is necessary because
USE_OPTION_TABLE is part of a `choice`.
[0]: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: I9e8f044077a5158650627a305c352cc9de578293
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90433
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Filip Gołaś <filip.golas@3mdeb.com>
In addition to adding all currently-known names for the boards, add SoC
names to baseboards to make finding boards based on SoC family easier.
Change-Id: I389f68f09409ce3eb51422dbcfe7e80d463a1594
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Build test the zstd code on qemu x86 and qemu aarch64.
Change-Id: Ib1f10b983492e01f74c7218e03e04615a41e7312
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89277
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds the option to compress ramstage and payloads with zstd.
zstd compressed ramstages are typically +5% bigger than lzma compressed
ramstages. The decompressor .text section grows by 20KiB and the
decompressor needs 16KiB more heap than the lzma decompressor.
To use less heap inside the zstd decompressor the build time define
ZSTD_DECODER_INTERNAL_BUFFER is used.
Quote:
The build macro `ZSTD_DECODER_INTERNAL_BUFFER` can be set to control
the amount of extra memory used during decompression to store
literals. This defaults to 64kB. Reducing this value reduces the
memory footprint of `ZSTD_DCtx` decompression contexts, but might
also result in a small decompression speed cost
TEST=Booted on Lenovo X220 with zstd ramstage showed no disadvantage
over a bigger internal buffer used.
TEST=Booted on Lenovo X220. The zstd decompressor is twice as fast
as the lzma decompressor.
cbmem -t shows:
- finished ZSTD decompress (ignore for x86) 79,444 (24,494)
- finished LZMA decompress (ignore for x86) 94,971 (45,545)
TEST=Booted on QEMU Q35, QEMU aarch64 virt, QEMU riscv RV64 with
zstd compressed ramstage.
Change-Id: Ic1b1f53327c598d07bd83d4391e8012d41696a16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69893
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define ENV_RAMSTAGE_LOADER in rules.h similar to ENV_PAYLOAD_LOADER
to simplify the current code and avoid code duplication when adding
zstd support.
Change-Id: I8c049c640b11c6f0b51e37dd2c368bb786ca9b0f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90153
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This adds zstd support to cbfstool. The code is taken from zstd-1.5.7
with modifications:
- renaming bits.h to zstd_bits.h to avoid conflicts with coreboot's
bits.h used on riscv
- renaming compiler.h to zstd_compiler.h to avoid conflicts with
coreboot's compiler.h
- Dropped all streaming API functions
- Dropped multithreaded support, since it's now unused
- Dropped local DDict support
zstd offers similar compression ratios to LZMA, but a vastly fast
decompress speed. Typically zstd results in slightly larger binaries
than LZMA. Whether zstd should then be preferred over LZMA depends on
a few things:
- Caching: When loading from memory mapped boot devices, zstd will read
the boot medium multiple times, while LZMA will not. If the memory
mapped boot medium is not cached zstd results in much slower
decompression.
- Boot medium speed: Often, but not always LZMA results in smaller
binaries. If the boot medium is the bottleneck, than loading smaller
binaries might actually be faster. On a fast boot medium (high spi
freq, using quad/dual io), the performance benefits from zstd might be
more substantial
- zstd decompression code has a much larger footprint than LZMA. If the
stage (postcar) is loaded in uncached memory the size increase might
slow things down.
On QEMU Q35 postcar .text section size doubled, while heap section
has growen by 50%.
- zstd uses a lot of .bss (CTX is about 32KiB large). This might not be
available in some environments.
Orignal commit from 2022 was using zstd-1.5.2. Updated to zstd-1.5.7.
Change-Id: I34508268f8767008ef25cb9e466d201345881232
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69753
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex, and MT62F2G32D4DS-031RF WT:C using spd-6.hex
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
H58G56CK8BX146 2 (0010)
K3KL8L80CM-MGCT 3 (0011)
MT62F1G32D2DS-031RF WT:C 4 (0100)
MT62F2G32D4DS-031RF WT:C 5 (0101)
BUG=b:447273470
BRANCH=firmware-trulo-15217.771.B
TEST=util/spd_tools/bin/part_id_gen ADL lp5 \
src/mainboard/google/brya/variants/pujjocento/memory \
src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
Change-Id: Ica96fefb3fb8b18ed693383641960c67e128e7e7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90454
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MT62F2G32D4DS-031RFWT:C in the memory_parts.json and re-generate
the SPD.
Micron: MT62F2G32D4DS-031RFWT:C
BUG=b:447273470
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2dc0151db31ed07c61454e800d539c9b546a1ea7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Newer gcov/lcov versions shipped in CI container images throw a warning
and thus cause the CI to fail. It's unclear how to fix this warning at
the moment, but gcov isn't critical anyway. So disable this specific
warning for now, so that we can roll out new CI images.
Excluding file '/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c'
lcov: WARNING: (inconsistent) /home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/libcbfs/cbfs.c:79: unexecuted block on non-branch line with non-zero hit count. Use "geninfo --rc geninfo_unexecuted_blocks=1 to set count to zero.
(use "lcov --ignore-errors inconsistent,inconsistent ..." to suppress this warning)
Excluding file '/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c'
[snip]
Message summary:
1 warning message:
inconsistent: 1
genhtml: ERROR: (corrupt) unable to read trace file 'build/coverage/tests.info': genhtml: ERROR: (inconsistent) "/home/coreboot/node-root/workspace/test_coreboot/payloads/libpayload/libcbfs/cbfs.c":77: function 'cbfs_unmap' is not hit but line 79 is.
To skip consistency checks, see the 'check_data_consistency' section in man lcovrc(5).
(use "genhtml --ignore-errors inconsistent ..." to bypass this error)
(use "genhtml --ignore-errors corrupt ..." to bypass this error)
make[1]: *** [tests/Makefile.mk:277: coverage-report] Error 1
make: *** [util/testing/Makefile.mk:103: what-jenkins-does] Error 2
Change-Id: I2c52c53fbe856a8bca062f34c576fdfda3818f2b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If the APs are much faster then the working hart, it is possible that it
will enter HART_SLEEPING state before the working hart checks whether or
not the APs woke up by checking the HART_AWAKE state.
One can reproduce this issue by adding the following print message and
testing it in QEMU. One will notice that it will get stuck.
+ printk(BIOS_SPEW, "waiting for hart %d\n", i);
while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != HART_AWAKE)
Fix it by adding another sync step at the end of `smp_resume()`.
Tested: QEMU RISC-V with -smp 64 parameter
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I1e0485831f71dde400d793b9f7bda88ae6519913
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Depending on the Kconfig, LAPIC may be in either xAPIC or x2APIC mode.
However, coreboot generates MADT LAPIC entries based on APIC ID rather
than currently enabled LAPIC mode. This resulted in LAPICs enabled in
x2APIC mode being described as xAPICs in MADT.
Create appropriate MADT LAPIC entries based on currently enabled mode
by calling is_x2apic_mode.
TEST=MADT describes LAPICs in x2APIC mode on Gigabyte MZ33-AR1, matching
the actually enabled LAPIC mode.
Change-Id: Iebbbca415f0b775339cbfab5c24848940d92878d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89475
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Makefile is patching the BIOS moudule base address and size so that
the openSIL knows where the reset vector resides. However, the printf
used for hex convertion is missing 0x prefix for hexvalue. Kconfig hex
values start with 0x prefix. Otherwise, there is a chance the bios_base
variable could be interpreted as decimal integer. This could result
in improper reset vector address being calculated in OpenSIL and APs not
able to be brought up.
Change-Id: Ib528491b266ec2e8d74b9c8713788f8f37037162
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89472
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
FWTS complains on HPET base not being found in DSDT/SSDT:
Test 3 of 4: Test HPET base in DSDT and/or SSDT.
WARNING: Test 3, Test skipped because HPET Device address was not
found in DSDT/SSDT.
Declare HPET device under LPC device to fix the issue.
TEST=Run FWTS on Gigabyte MZ33-AR1 and see no error in HPET tests.
Change-Id: I68b872291dc93320e7a0b33a79e3336e1372b178
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89924
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.
[1] https://docs.amd.com/v/u/en-US/48882_IOMMU
Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Configure the touchpad I2C bus high and low time.
BUG=b:466136598
TEST=Build and boot to OS in kodkod.
kodkod:/ # getevent
add device 2: /dev/input/event4
name: "Elan Touchpad"
Change-Id: I5c996ccf69e8dfe1485c7161ea2efd5579190975
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The DSM methods already have the full ASL generated by the acpigen
calls in a comment above the function, so there's no need for line-
by-line comments for the acpigen calls. Keep the comments for
acpigen_pop_len() as they do enhance readability.
TEST=n/a, non functional change
Change-Id: I95bbc0b36706a45883ea50b7947c6c0235f546f7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90544
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for parallel charging by configuring PMC8380F GPIO07
and GPIO09. These GPIOs are configured as outputs with inverted
logic. A new Kconfig option MAINBOARD_SUPPORTS_PARALLEL_CHARGING
is introduced to allow variants to opt-in to this configuration.
BUG=b:468120472
TEST=Build Google/Quartz.
Change-Id: I0126d987650c660e305f704708c09356908633e4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90514
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the qclib_mainboard_override hook to enable Power Delivery
negotiation if no battery is detected, even in normal boot mode.
This allows the system to negotiate higher power levels when
running solely on AC power.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
Change-Id: If1660e4c50575eb4b6d5af606c35accdb4c67982
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Implement the qclib_mainboard_override hook to enable Power
Delivery negotiation when the system boots into off-mode charging
or low battery mode. This ensures proper charging levels are
negotiated early in the boot process.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: I6c4b861862d739b002c4043ade21328e02186bbd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90513
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move Gen4 SSD power enable (GPP_H18) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.
Changes:
- Enable GPP_H18 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
- Remove duplicate GPP_H18 configuration from gen4_ssd_pads
- Remove GPP_H18 from ramstage gpio_table
BUG=None
TEST=Build Ocelot and check PCIe link speed over multiple cold boot
iterations and ensure that the link is trained to maximum capability.
Test Steps:
- Cold reboot the system: ectool reboot_ec
- Check the current link speed and max link speed:
cat /sys/bus/pci/devices/0000:00\:1c.0/current_link_speed
16.0 GT/s PCIe
cat /sys/bus/pci/devices/0000:00\:1c.0/max_link_speed
16.0 GT/s PCIe
- Repeat these steps for multiple iterations and ensure that current
link speed is equivalent to max link speed.
Change-Id: I31a0a92c168e9c851246359e69faabd786248b5c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90363
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each error source descriptor basically has these values at the
beginning. The error source descriptors are added in the follow up
patches.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic6873cb8cf7373435be3ce26382aa8ae37cd5938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add validation checks in camera_enable() for required parameters:
- ssdb.lanes_used
- ssdb.platform
- rom_address (when rom_type is set)
- vcm_address (when vcm_type is set)
Remove default values for ssdb.platform and ssdb.lanes_used from
camera_fill_ssdb_defaults() since these parameters are now required
and validated. All boards in the tree explicitly set these values
in their devicetree configurations, so the defaults were never used.
Also remove the unused cio2 and cio2_config variables that were only
used for the lanes_used default logic.
Change-Id: Idcb84c25b94ed9259698aafba201cc4f4e0f1af7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90517
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for non-VGA devices (e.g., Intel IPU) in the generic
graphics driver by:
- Adding DOD_NONVGA bit definition per ACPI spec 6.5 table B-2
- Adding non_vga_device boolean field to device config structure
- Increasing device array size from 6 to 7 to accommodate IPU
- Updating ACPI _DOD generation to use DOD_NONVGA flag for non-VGA
devices instead of DOD_FW_DETECT
This allows proper ACPI enumeration of non-VGA devices whose power
is related to the VGA device, such as Intel Image Processing Units.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I60472e1232959fe407f63b4b8e6bffba995e7f79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90516
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Refactor the MIPI camera driver to support two ACPI device generation
modes via a Kconfig choice:
1. Windows/Linux mode (MIPI_ACPI_TYPE_WINDOWS_LINUX): Generates a
single ACPI device for the camera sensor and any associated VCM or
NVM devices on the same I2C bus. The IPU ACPI device is attached to
the iGPU, not standalone. This is the preferred method for Windows
and mainline Linux.
2. ChromeOS mode (MIPI_ACPI_TYPE_CHROMEOS): Generates separate ACPI
devices for each camera component (sensor, CIO2, VCM, NVM). The IPU
ACPI device is generated separately from the iGPU. This maintains
compatibility with the existing ChromeOS-style setup.
The implementation uses runtime conditionals to select between the two
modes. Common helper functions are shared between modes, while device-
specific logic is conditional based on the selected ACPI type.
The default selection is MIPI_ACPI_TYPE_CHROMEOS for ChromeOS builds and
MIPI_ACPI_TYPE_WINDOWS_LINUX otherwise.
Change-Id: I0bc4894aff04d6b296011e85d790d624890da055
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90522
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add support for Computer Vision Framework Support DSM UUID with ACPI-
compliant query handling and ASL documentation. Currently we are
always returning Zero (unsupported/disabled), but support will be
added in future patches.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I6db88285d757826fa0f3eb5aa4bb1cc4176b95b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90490
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add camera_generate_dsm_i2c_v2() to support the I2C V2 DSM UUID
(5815c5c8-c47d-477b-9a8d-76173176414b) which returns I2C device
addresses in a buffer format, rather than individually. Includes
ACPI-compliant function query handling (Arg2==0) and ASL code
documentation.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: Ifd35b53b21d0d1be9e9802059c724bf544ca1a1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90489
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename UUID macros to match external conventions used in Linux kernel
and Windows Camera DDK:
- SENSOR_NAME_UUID -> UUID_DSM_SENSOR
- SENSOR_TYPE_UUID -> UUID_DSM_I2C
Rename functions for clarity:
- camera_generate_dsm_sensor_name -> camera_generate_dsm_sensor
- camera_generate_dsm_sensor_type -> camera_generate_dsm_i2c
Add ACPI-compliant function query support (Arg2==0) to sensor DSM,
returning bitmask of supported functions as required by ACPI spec.
Add ASL documentation comment blocks above each DSM generator function
showing the generated ACPI code structure.
Improve variable naming (i2c_dev_count, i2c_dev_idx) for readability.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I38facaf85ea59aa82621d82555858c0d72b1ee30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Refactor camera_generate_dsm() to call separate functions for each
DSM UUID type, improving code organization and maintainability, in
preparation for adding the generation of additional DSM UUIDs in
subsequent patches.
This is a non-functional change.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I8b3fb6e3004ea30aa7c11217c9971bddb977ded5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add ssdb.rom_type and rom_address registers to board variants for MIPI
camera sensor SSDB settings, which are necessary for the Intel driver
stack under Windows and mainline Linux. A handful of boards, mostly not
released to the public, include a commented-out placeholder as ROM type
24C1024 is currently unsupported.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I16b44609c1b07ac686d67cc59b4b5311495117ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90486
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Apply the change of commit a97fb7f960
("mb/google/volteer/variants: Update Power Limit2 minimum value")
to drobit since it looks like it has been forgotten. It is the
last variant where pl2 min != max.
TEST=Build and boot google/drobit and verify sane clock speeds and
tempoeratures under full CPU load.
Change-Id: I7b09825ebd95fd2795408cdaa0396bbf19baded9
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90501
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
