Swathi Tamilselvan 2f9b4ad6a5 soc/qualcomm/x1p42100: Add DFSR table configuration support ... Add support to configure DFSR table, introduce qupv3_clock_v2 structure to calculate register addresses for serial engines 2 and 3. Update CBCR registers to use the new structure for QUPv3 clock enablement. BUG=b:444617760 TEST=Create an image.serial.bin and ensure it boots on X1P42100. Dump DFSR registers for corresponding QUP and check if values are updated properly into correct register address. Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>		2025-11-25 16:47:20 +00:00
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common	soc/qualcomm/x1p42100: Add DFSR table configuration support	2025-11-25 16:47:20 +00:00
ipq40xx	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
ipq806x	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qcs405	soc/qualcomm: Move common region macros to soc/memlayout.h	2025-08-17 01:10:35 +00:00
sc7180	soc/qualcomm: Move common region macros to soc/memlayout.h	2025-08-17 01:10:35 +00:00
sc7280	soc/qualcomm: Move common region macros to soc/memlayout.h	2025-08-17 01:10:35 +00:00
x1p42100	soc/qualcomm/x1p42100: Add DFSR table configuration support	2025-11-25 16:47:20 +00:00