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soc/qualcomm/x1p42100: Reserve DDR carveout region

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Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The
carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is
the DRAM size. This region is protected by QTEE and must remain
reserved to prevent access by other components.

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified carveout region reservation via depthcharge serial log.
Prior to reservation, the memory wipeout range was [0x000000f61f7920,
0x000000ff800000). After reserving the carveout, the range is reduced
to [0x000000f61f7920, 0x000000f7c00000).
```
Wipe memory regions:
        [0x00000080000000, 0x00000080a00000)
        [0x000000815a0000, 0x00000081a00000)
        [0x00000081cf4000, 0x00000081e00000)
        [0x00000082800000, 0x00000085380000)
        [0x00000085f80000, 0x000000866c0000)
        [0x00000091380000, 0x000000c72c4000)
        [0x000000c7800000, 0x000000d8000000)
        [0x000000d9600000, 0x000000f1000000)
        [0x000000f61f7920, 0x000000f7c00000)
        [0x00000880000000, 0x00000c00000000)
```

Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Swathi Tamilselvan 2025-10-13 16:30:16 +05:30 • committed by Subrata Banik
commit 5271ac7ac5
2 changed files with 11 additions and 0 deletions
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2
src/soc/qualcomm/x1p42100/memlayout.ld
View file

@ -23,6 +23,8 @@
* 0xFFE00000 +----------------------------------------------------------+ | |
* | dram_llcc_lpi | | |
* 0xFF800000 +----------------------------------------------------------+ | |
* | dram_acdb | | |
* +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0xDF4C0000 +----------------------------------------------------------+ | |
* | dram_ta | | |

9
src/soc/qualcomm/x1p42100/soc.c
View file

@ -14,6 +14,11 @@ static struct device_operations pci_domain_ops = {
.enable = &qcom_setup_pcie_host,
};
static uint64_t calc_acdb_carveout_size(void)
{
return ((((region_sz(ddr_region) / GiB) * 11) / 2 + 36) * MiB);
}
static void soc_read_resources(struct device *dev)
{
int index = 0;
@ -43,6 +48,10 @@ static void soc_read_resources(struct device *dev)
reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil));
reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta));
/* ACDB carveout region located at 0xFF800000 - (n*5.5 +1+32+3) where n is size of DDR */
reserved_ram_range(dev, index++, (uintptr_t)(_dram_llcc_lpi - calc_acdb_carveout_size()),
calc_acdb_carveout_size());
reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi));
reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem));
}