Explain when the MBOX_PSP return codes are send and which behaviour
is invoked by the PSP when seeing such return codes.
Change-Id: Ibe7ceb5d7cd025f3b3ab0c9167d23f6eb664c165
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When coreboot is operating on the SPI flash lock the bus by
setting SPI_SEMAPHORE_BIOS_LOCKED in SPI_MISC_CNTRL. This prevents
SMM from accidentally corrupting SPI CTRL registers, even though
SMM backups and restores SPI CTRL registers.
TEST: Booted an AMD glinda and observed SMM not accessing the SPI
controller as long as ring 0 is operating on it.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaeda356b55d3f203c75f4056da7bde2abacebc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently the PSP SMI handler works only if you are lucky. Since
ring 0 can start SPI flash transactions any time and the PSP SMI might
happen shortly after that, the SPI controller or SPI flash might be
busy. When the SPI flash is busy it cannot process certain commands,
for example reading the contents, causing the SPI flash memory map
to return all 0xffs.
By introducing the AMD fTPM code the PSP SMI happens more often at
boot and uncovered this issue. This issue was found when deleting
the MRC cache, which takes quite long, while the PSP SMI tried to
access the SPI flash. Adding small delays, as introduced by
CONSOLE_SERIAL, resolved the issue.
Add code to check if the SPI controller and the SPI flash are busy.
If so tell the PSP SMI to retry at a later point in time.
TEST: AMD glinda boots with CONSOLE_SERIAL disabled.
Logging to CBMEM shows that the PSP SMI is fired 10 times
before the SPI flash no longer reports that it's busy.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9122165e7c60b7c288d5b61b80d4cb582901841c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for MIPI panel on padme and enable TM_TL121BVMS07_00C as
the default panel. The panel uses AW37503 as the bias IC, with supply
set to ±5.9V. Add AW37503 initialization and power-on sequence are
configured according to the specification.
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
BUG=b:432353024
TEST=emerge-skywalker coreboot
Change-Id: I37a1c0352a8619ce5b10727cdeef524ccb1107ef
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89218
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the schematic diagram of lapis, refer to
the design of fatcat and modify the gpio order of mem_id.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I715634e231725bbd009b35a0c520d19a894f569c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Add HYNIX H54G46CYRBX267 as id 1, and add Samsung K3KLALA0EM-MGCU
as id 2, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
BUG=b:438785495
TEST=Use part_id_gen to generate related settings
Change-Id: I4179e31222d461b93f81c784511cc34071c10257
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This CL follow Commit 2ba74b8c18 ("mb/google/brox: Hint romstage init
about upcoming reset") CB:84937 to add PDC FW hash in variant.c to hint
romstage init about upcoming reset.
BUG=b:445606386
TEST=Build Caboc BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ie029bf7faf991f520c42ffe22e610291ba98e078
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89190
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently check_auxfw_ver_mismatch() expects the hash file to contain
only auxiliary firmware version and hence strictly checks for the size
of the auxiliary firmware version (3 bytes).
However, in some cases the hash file might contain other information
such as config_name.bin name which increases the hash file size.
Accommodate this scenario by checking the hash file size greater than
or equal to auxiliary firmware version size.
BUG=b:445606386
TEST=Build BIOS image with hash size of 3 and 11. Ensure that the
hints are provided correctly and 2 redundant resets are filtered out.
Change-Id: I287079cfc3cfbc75575ecde0603b98c57b42aa24
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Adds the `google_chromeec_ap_poweroff()` helper function to the ChromeEC
driver.
This new API wraps the `EC_CMD_AP_SHUTDOWN` command and sends it to the
Embedded Controller (EC). This provides a cleaner, standardized way for
other coreboot components to initiate an Application Processor (AP)
power-off sequence via the EC.
After sending the shutdown command, the function calls `halt()` as the
AP is expected to power down immediately after the EC processes the
command.
BUG=b:439819922
TEST=Verify shutdown on Google/Quenbi.
Change-Id: Iace6a66972791bb7acdb978dfeea67b6ff0fec68
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89223
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
60aa7ccea9c include/ec_commands.h: Avoid lint errors
The original include/ec_cmd_api.h version in the EC repo is:
f47d8af4fbb include/ec_cmd_api.h: Define new API for EC_CMD_AP_SHUTDOWN command
Change-Id: I31d08bf4a0318ca3ba8c5bb5563acfe65830523b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit updates the DDR5 memory initialization parameters for the
Intel PTLRVP mainboard. Specifically, the ChannelToCkdQckMapping and
PhyClockToCkdDimm settings are overridden to ensure accurate mapping of
memory channels and PHY clocks to their respective Clock Driver and
DIMM connections.
BUG=none
TEST=Boot the PTLRVP board with DDR5 memory and verify memory
initialization.
Change-Id: I1be0a66a40e2613f10426dacd5494e345c5579db
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change allows flag to be overridden via devicetree, instead of
relying on the default value in alc711_slave. It helps fix the
missing event issue when plugging or unplugging the 3.5mm headphone
jack.
TEST=Verified build and boot with ALC721.
Headphone path switches successfully via audio jack event.
Change-Id: Ib766363fd7462bb03905fa6cba805b27d10efa04
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88867
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic diagram, lapis is designed
with five temperature detection nodes, so the initial
thermal strategy was updated.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change corrects the ACPI wake event mapping for the gspi0 device,
ensuring the wake signal is routed through GPE0_DW2_19 instead of
GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in
devicetree.cb
Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The list of changes are as follows
1. Modified USB2 port 7 from M.2 WLAN to discrete Bluetooth device.
2. Updated both Type-C ports to OC_SKIP to reflect virtual ports.
3. Adjusted Type-C port ACPI group assignments for USB3 ports.
4. Reduced display device count from 5 to 4 by removing DD04.
5. Updated comments and port usage to clarify Type-A and Type-C port
assignments.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I1e8cc92463a462c9baa78cd6d79637004340f7e2
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The FP_PRESENT probe is not required for the ISH device as they are not
in the same BDF. ISH is in the rootport 0:18:0 and gspi0 is 0:30:2.
Change-Id: I00ee0825f60719fb5a34a215780a14645def8b4c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Use fw config bit 15 to identify different ish files when enable
or disable tablet mode.
TABLET_ENABLE : pujjolo_ish.bin
TABLET_DISABLE : lite_ish.bin
BUG=b:432649211
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version
and test warmboot/coldboot/suspend pass.
Change-Id: Iffaadd5c772be6306cdcec08385de90c089f0489
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89215
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).
The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.
The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.
w/o this patch
```
[ERROR] Unable to load previous training data.
```
w/ this patch
```
[WARN ] qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```
Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Ocelot uses the CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
because the hardware does not have DRAM ID straps, but this option was
designed for boards that would only ever have a single memory option.
In order to support multiple memory parts, we need to create a table
that maps memory part number to DRAM id so that we can select the
correct SPD for the memory, and then override the variant_memory_sku()
routine so that we can determine and return the correct DRAM id for
the memory part number specified in the CBI.
BUG=b:443646405
TEST=Change DRAM part number in CBI to "H58G66BK7BX067", reboot ocelot
and verify the AP boot logs show that the SPD index = 1.
Change-Id: I18ba6c4891c6053f40e99dcde8a06b9efc1d95f4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit updates the PCIe root port configuration for the SD card
interface in the overridetree.cb file for the Ocelot variant.
The reference is changed from `pcie_rp5` to `pcie_rp6`.
BUG=b:440042829
TEST=Boot the device with the updated firmware and verify that the
SD card is enumerated under pcie_rp6
Change-Id: I2b3c0b6e19409fef933aa7dc06f5df035f620738
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88873
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to build for PantherLake with TME disabled, key generation
needs to depend on TME Kconfig.
Change-Id: I0af438e279f422292302387442489bcbc1b1605f
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89226
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Set up all output GPIOs. The initial values are set consistently with
the values in kernel to avoid voltage steps in the bootup process. The
GPIOs are sorted by their EINT IDs.
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: Iacc1808108a33ca66f06ba5b3a4b082ed4e2673f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define all GPIO pins in gpio.h by their names defined in the AP pinmux
table. For example, the name of GPIO12 is "EN_PWR_FP".
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: I3936cc667d3695ff1609c3fd0fac59a204d511a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89285
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Camera sensor gets enumerated even if the hardware is not connected and
makes it available for the user, leading to a black screen when the user
tries to open the camera.
This commit changes the probing power state for the OV13B Camera Sensor
to the D0 Power State in order for the driver to validate the physical
hardware connection. This change helps prevent unnecessary enumeration
when hardware is not connected.
TEST=On a Fatcat device with an OV13B camera sensor disconnected, the OS
does not offer to use this video device.
Change-Id: Iabd8ffa6fd50367ff77325a2e1d9ae05e31eac93
Signed-off-by: Venturi Naveen <venturi.naveen@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The ITE EC may take more than 2 seconds to complete EC FW
hash calculation in some corner cases. For example, boot with
a dead battery, EC even takes more than 10 seconds to complte
the hash calculation. Extend the timeout from 2 seconds to 12
seconds to cover the ITE EC cases, it should not impact boot
time and functionalities.
BUG=b:445034279, b:444392807
Change-Id: I4f6e23dc3096cbba04c33c8f3cc36c90aa83462a
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89293
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides `SkipExtGfxScan` UPD as the Fatcat device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
TEST=Able to save ~10ms+ boot time on google/fatcat.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
50b8 680462 42 76f18bda-2195-4fb6-9a940e0bacdeecab
50b9 696649 16187 76f18bda-2195-4fb6-9a940e0bacdeecab
With this patch:
`CheckOffboardPcieVga` is not getting called.
Change-Id: I198a99ac5596ff98a9cc673dbd84889d7c5386cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88888
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The multi-line `$(eval $(call ...))` for adding the default BMP logo
contained extraneous whitespace. This included a leading space before
`logo.bmp` and, more critically, a newline, tab, and non-breaking
spaces before `CONFIG_BMP_LOGO_FILE_NAME`.
This problematic whitespace was passed as part of the third argument
(`$(3)`) to the `add_bmp_logo_file_to_cbfs` macro. Inside the
macro, the deferred variable expansion `$$($(3))` would fail because it
was searching for a variable name with leading non-breaking spaces.
This resulted in the `logo.bmp-file` variable being set to an empty
string, causing a build failure when the cbfs tool tried to find the
logo file.
This commit collapses the function call onto a single line to remove
all line continuations and problematic whitespace, ensuring the
correct, clean arguments are passed to the macro.
BUG=b:444655145
TEST=Able to verify that 'logo.bmp' is added correctly to the CBFS,
and also verify the FW splash screen visible on redrix device.
Change-Id: Ia91b927dd0248909fc1c75534a7e7b00dab0fc09
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit addresses a potential low power state over-consumption
issue. This issue could arise if SPI DMA has been locked down while a
transfer was still marked as active, typically if a SPI DMA transfer
failed and hung.
The fast_spi_dma_lock() function now checks if a DMA transfer is ongoing
and ensures that it is marked as complete before locking the DMA control
register.
Change-Id: I5e08991b2160a43013b129d302c46fc229f2286d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88913
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue with the 3.5mm headphone jack on the I2S codec AIC not detecting headphone plug/unplug events.
Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
TEST=After booting to OS, plug and unplug a headphone to the I2S codec add-in card, headphone is getting detected.
Change-Id: I263f7e9e2da0440801404dddfcf534b9ea79d470
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Add H58G66CK8BX147 memory part as DRAM ID 2.
BUG=b:446088494
TEST=None
Change-Id: Ice18fd3209b0552be8f8612aaa3ff30ba76c8b83
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89269
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add H58GE6AK8BX104 memory part as DRAM ID 3.
BUG=b:445211686
TEST=None
Change-Id: I10876384f67d9201b14dc19213cfc77d62213070
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Add H58GE6AK8BX104 in the memory_parts.json and re-generate
the SPD.
BUG=b:445211686
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I4bf1d0fc3325ec2d4247a0263a44a81934a3a90e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
smbios_mainboard_enclosure_type() is not linked when SMBIOS
is disabled. Fixes a linker error when the user disabled SMBIOS
table generation in Kconfig.
Change-Id: Ic3e70c658d01a839eb37f0862f31ee9f65a84300
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89280
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel id is sampled with AUX_IN4 (PANEL_ID_LOW_CHANNEL) and AUX_IN5
(PANEL_ID_HIGH_CHANNEL). Introduce 3 voltage thresholds to distinguish
different panels:
- v < 0.5V -> id = 0
- 0.5V ≤ v < 1.0V -> id = 1
- v ≥ 1.0V -> id = 2
BUG=b:433405205
TEST=Tested by booting with the payload and confirming the kernel get
the correct skuid.
Change-Id: I590a19b6cade3cae15a58a9b3541ff471e038435
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89217
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure eMMC DLL tuning values for Kaladin project.
Sending different speed TX/RX command/data signal to eMMC and check the response is success or not.
Based on the test result from each eMMC source used in the project as the tuning value.
Refer to EDS-Vol2-42.3
BUG=b:440126134
TEST=Pass on 2500 cycle of cold boot stress on all eMMC sku
Change-Id: I6295b36500053356a28d51b48a9758ee32b82b53
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89034
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Add TM panel TM_TL121BVMS07_00C serializable data to CBFS.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
[INFO ] CBFS: Found 'panel-TM_TL121BVMS07_00C' @0x81f80 size 0x77
in mcache @0xfffdd540
BUG=b:428854543
TEST=build and check the CBFS include the panel
BRANCH=skywalker
Change-Id: I50e56aef1576722b7f2fb811c5d9df2a5697edae
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89216
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Due to a GPIO configuration issue, the buzzer continues to operate
after the OS boots, producing noise from the capacitor.
The buzzer is driven by the GPIO pin and P_MOS, so it should be set
to high in the coreboot.
For the schematics, please refer to b:442747023#comment4.
BUG=b:442747023
TEST=Can not hear abnormal noise.
Change-Id: I720e5cc0e8c499d654a2b3002c3647d37e2ae8d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89035
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only need the first 512, so skip reading the rest to save
boot time. With 96GB, it reduces time in FSP-M from 906,307
to 326,302.
Change-Id: Ia226402fdf613ba4b851fa9c4c7d9354d599be7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89220
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Select the newly introduced `HAVE_CBFS_FILE_OPTION_BACKEND` capability
for the Qualcomm x1p42100 SoC family.
This SoC is used in ChromeOS devices that rely on the CBFS file backend
to store and retrieve runtime configuration options (like the QCLib
configuration data). Selecting this capability ensures the correct
option backend is chosen in the Kconfig `Option backend to use` choice.
TEST=Build and boot a board using the x1p42100 SoC (e.g., bluey).
Confirm the `CONFIG_USE_CBFS_FILE_OPTION_BACKEND` option is enabled
in the build.
Change-Id: Ie0dee155a504da215669a79d7100cdbaf97d5261
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
