Fix regression introduced in commit 0351872731
("arch/x86: Add breakpoint to stack canary").
romstage_main writes to the stack-canary, but since that's expected
temporarily disable the breakpoint. This only caused a warning on
platforms that do select IDT_IN_EVERY_STAGE, since those install the
stack canary breakpoint.
TEST: No more exceptions are printed in romstage when IDT_IN_EVERY_STAGE
is enabled.
Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The mainboard code relies on IPMI communication with the BMC.
Since the x86 and BMC start booting at the same time on ACPI G3
exit and the x86 is a bit faster, wait for the BMC to signal it's
done booting by pulling GPP_F4 low.
Fixes lots of error messages in coreboot about not working IPMI:
[ERROR] wait_ibf timeout!
[ERROR] IPMI START WRITE failed
[ERROR] ipmi_kcs_send_message failed
TEST: Once GPP_F4 is low IPMI communication over the KCS is also
working on ocp/tiogapass.
The log contains the line:
[DEBUG] BMC ready after 125560 ms
Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85492
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 559910 Intel Connectivity Platforms BIOS
Guideline revision 8.2 and 9.2 specifications, both revision 0 and 1
are supported and share the same structure.
BUG=b:346600091
Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85586
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage
hook and introduce early_pch_init() to do PCH init in romstage before
FSP-M runs.
Move PCH specific code into early_pch_init and call it from common code.
Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85505
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no
official bit in the IFD to disable it. The device is disabled
early to:
1. Prevent FSP from seeing the device being present. It could keep
an internal state that the device is working.
2. Prevent FSP-M from trying to detect codecs. This would increase
boot time.
3. Prevent FSP from becoming confused or crash when the device is
suddently missing as disabled by a ramstage PCI driver.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85496
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the debug code as there were unexplainable stack corruptions
detected on some platforms.
No problems were observed on:
- QEMU
- Xeon-SP
Change-Id: I1f1b9f01af7fbb0c19becf6ea53d436898584c5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply ISH_FW_VERSION in Kconfig to improve boot time.
It won't do some ISH init task without the config on UFS sku and
cause boot to kernel time over 1.55 sec from G3 boot.
BUG=b:364971947
BRANCH=firmware-brox-16080.B
TEST=cbmem -c | grep "ISH version" -> ISH version: 5.4.2.7780
Boot to OS on jubilant, run bootperf test of G3 boot.
Confirm the test result is pass.
Change-Id: I31db0925a81b6ec68ee6afcb262e540ba7db206a
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update header files for FSP for Meteor Lake platform to version 4122_21,
previous version being 3471_91.
FSPS:
1. Added UPD's ThcMode, ThcWakeOnTouch
2. Reserved bit changes
FSPM:
1 Added PchHdaSubSystemIds
BUG=b:329548127
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I4a1164060f7e91f8fa4ada60421bf87fb17ad541
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84656
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Route IRQ for on-chip end-points only (e.g. 00:1f.4
i801_smbus)
IRQ routing for devices under root ports needs additional
swizzle per decided by root port configurations, which will
postponed to later till there is actual usage.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch introduces logging for the ELOG_TYPE_FW_CSE_SYNC event. This
event logs data related to CSE synchronization, along with the relevant
boot stage information.
BUG=b:305898363
TEST=boot verified on google/rex0 and google/rex64
Change-Id: I4d6d3c4e07ab8677feb6a8acf8d4c6604ab704b8
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85218
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new event log type, ELOG_TYPE_FW_CSE_SYNC. The
purpose of this event type is to log successful completion of CSE
synchronization.
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
Change-Id: Id73fa3a77e5fbbae5c61dfb30ae26b4ba3dca6ab
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85217
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ImguClkOutEn parameters are required in pantherlake, therefore,
avoid disabling the IMGU CLKOUT FSP UPDs.
BUG=b:381044394
TEST=Able to see FSP-M UPDs for google/fatcat where IMGU CLKOUTs are
not disabled with this patch.
Change-Id: Ieb022e6dc0b64106ff30f56cd17f9f219276785f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85588
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and
`DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options
for the Pantherlake SOC.
These options are causing false positive stack overflow detections,
leading to unnecessary debugging.
w/o this patch:
stack corruption before for verstage and romstage early.
Failed to create address zero instruction fetch breakpoint
Failed to create stack canary breakpoint
...
...
Stack corruption detected at rip: 0xf983007a
Stack corruption detected at rip: 0xf983007a
Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85584
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Format bare URLs as links so that they are rendered as hyperlinks
instead of plain text.
Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85433
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in memory config based on the schematic_20241203.
BUG=b:380476928, b:380789023
TEST=emerge-nissa coreboot
Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85542
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This change enables the GPP_F9 GPIO, which controls the SLP_S0_GATE_R
signal and subsequently the SYS_SLP_S0IX_L signal.
By enabling GPP_F9 early in the boot process, we ensure the panel is
powered on correctly and able to render the eSOL message.
BUG=b:372737590
TEST=Verified panel power-on by observing eSOL during build on
google/marasov.
Change-Id: I727a72d9583575b2bbebe2c3b75c980170dd36b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The GPP_F23/ISH_GP_9A pin receives the lid open/close signal from
SMC_LID. This pin is not utilized in the AP firmware stack; however
the ISH firmware requires this signal for its tablet mode support.
Therefore, we configure this pin as an ISH GPIO.
BUG=b:370984186
TEST=Build and flash CB; run ISH main firmware; read this pin and
verified it returned the correct value.
fatcat-rev257 ~ # ectool --name=cros_ish gpioget lid_open
GPIO lid_open = 1
Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to its
SRAM space and then enable it.
It takes 20 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314
mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes)
TEST=can see the sspm logs.
BUG=b:372173976
Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0
Signed-off-by: Kenji Yu <kenji.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The patch disables Tccold Handshake to prevent possible display
flicker issue for jubilant board. Please refer to Intel doc#723158
for more information.
BUG=b:383433239
BRANCH=firmware-brox-16080.B
TEST=Boot to OS on jubilant, verify the display is without flicker.
Change-Id: I4f22067b81fa1b1b9addd7d1f49de59136d221c0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85555
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
After modified the settings, it could be met the time sequence for
this ILIT2901 touchscreen specification via our EE's measurements.
1. ILIT2901 Specification: ILI2901A-A202 Data Sheet_V1.2_20240128.pdf.
2. Double delay RST time to 12ms.
3. F/W calibration delay time is about 700ms after RST high.
The tuned firmware version is 005c_0700.0000.0000.0006.bin.
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Verified the sequence correctly by EE.
Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Implement PMIF driver for communication between SoC and PMIC. Develop
SPMI driver for communication over the SPMI bus. Add necessary
configurations and base addresses to support PMIF.
TEST=build pass, check boot log with:
[INFO ] mtk_pmif_init: SPMI_MASTER_1, 0
[INFO ] mtk_pmif_init: SPMI_MASTER_0, 0
BUG=b:317009620
Change-Id: I232015f45735ee5278b09d0352410617a1565177
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85126
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change simply replaces 0x80 with a top level constant called
ACPI_NOTIFY_CROS_EC_MKBP. There are no functional changes.
BUG=b:343288326
TEST=Build
Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Add GBTR Method, which gets the state of the RF Kill pin. Unlike
the VGPIO, this can be used for both CNVi and full PCI wireless
cards.
Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`acpigen_soc_get_tx_gpio` will put the result into Local0, rather than
emitting it as a byte so adjust the function accordingly.
Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This resource is applicable to S0, as it can be used to reset
the wireless and for RTD3, so change it from S5.
Change-Id: I9ae710ef452c717ec414324d2847bf3218fd62d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:383032918#comment1
BUG=b:383032918
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85535
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
We use ALC3204 as HDA codec on uldrenite, add the verb table
by Realtek.
BUG=b:374203133
TEST=emerge-nissa coreboot
Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a generic optimization to calculate a machine-word-sized
"wide sum" for the ipchksum() algorithm. This is often not as
efficient as handcrafted assembly (about half as fast on arm64 and
x86_32, about the same speed on x86_64), but likely still much better
than nothing on architectures that we don't have handcrafted assembly
for.
Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80304
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek booker (the customized ARM CI-700) is a high-performance
interconnect architecture designed for multi-core processor systems,
providing high bandwidth, low latency data transfer. And booker mainly
uses CHI protocol, but doesn't support coherence (which is achieved
through ACP solution). Additionally, the booker also uses other
protocols such as AXI, which translates CHI transactions into EMI's AXI
transactions.
Currently, the mt8196 booker only uses the functions of SLC CMO routing.
If downstream SLC needs CMO command propagation from the DSU, it is
needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of
each SBSX node in order to propagate the CMO command.
Increase the bootblock size from 75K to 78K to support booker.
TEST=build pass, check boot log with:
[booker_init] AP hash rule: 0xbe00.
BUG=b:317009620
Signed-off-by: Dehui Sun <dehui.sun@mediatek.corp-partner.google.com>
Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Once the MPLL has been initialised, convert the timings from the SPD to
be in DCLKs, which is what the hardware expects. In addition, calculate
the values for tREFI and tXP.
Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Move PCU specific code into separate files:
- PCUs registers are now locked by the PCI driver final call
- set_bios_init_completion() is not part of PCU1 driver
- Integrate config_reset_cpl3_csrs() into PCU driver
TEST: Still boots on ocp/tiogapass.
Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Match function name "init" with "remove" by renaming all
*_breakpoint_disable() to *_breakpoint_remove().
Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85540
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to debug stack smashing add a write breakpoint to the
stack canary (at _stack or _car_stack) and print the IP when the
stack canary is written.
TEST: Wrote to address _stack in ramstage and got the EIP of the
code that smashed the stack canary.
Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following functions are added:
_create_buffer_field
acpigen_write_create_buffer_byte_field
acpigen_write_create_buffer_word_field
acpigen_write_create_buffer_dword_field
acpigen_write_create_buffer_qword_field
These functions are to generate:
CreateByteField (<namestring> , offset, <field name>)
CreateWordField (<namestring> , offset, <field name>)
CreateDWordField (<namestring> , offset, <field name>)
CreateQWordField (<namestring> , offset, <field name>)
NOTE:
There are set of acpigen_write_create_[byte/word/dword/qword]_field
functions already, but the field can only be created from Arg[n] or
Local[n] variable objects. A Name object must be first assigned to such
variable. The new functions here will allow us to create field directly
from Name object.
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85197
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit enables the Dynamic Platform and Thermal Framework (DPTF)
for the fatcat board.
DPTF is a system management framework that allows the board to
dynamically adjust its power and thermal settings based on the system
load and thermal conditions. This can help to improve the board's
performance and battery life.
The following changes were made to enable DPTF:
- Added the Intel DPTF driver to the board's Kconfig file.
- Overrode the default DPTF settings in the fatcat variant
overridetree.cb file.
- Enabled the DPTF policy on the baseboard.
Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
