Docs: Convert bare URLs into hyperlinks

Format bare URLs as links so that they are rendered as hyperlinks
instead of plain text.

Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85433
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/getting_started/kconfig.md

@@ -1172,13 +1172,13 @@ vim-common), but most editors do not.
 
 ### ultraedit:
 
-https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew
+<https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew>
 
 
 
 ### atom:
 
-https://github.com/martinlroth/language-kconfig
+<https://github.com/martinlroth/language-kconfig>
 
 
 ## Syntax Checking:
@@ -1217,7 +1217,7 @@ in.
 ## License:
 This work is licensed under the Creative Commons Attribution 4.0 International
 License. To view a copy of this license, visit
-https://creativecommons.org/licenses/by/4.0/ or send a letter to Creative
+<https://creativecommons.org/licenses/by/4.0/> or send a letter to Creative
 Commons, PO Box 1866, Mountain View, CA 94042, USA.
 
 Code examples snippets are licensed under GPLv2, and are used here under fair

Documentation/infrastructure/services.md

@@ -41,7 +41,7 @@ stating:
 
 ### Gerrit user avatar
 To setup an avatar to show in Gerrit, clone the avatars repository at
-https://review.coreboot.org/gerrit-avatars.git and add a file named
+<https://review.coreboot.org/gerrit-avatars.git> and add a file named
 $your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)).
 The image must be provided in JPEG format, must be square and have at most 50000
 bytes.

Documentation/mainboard/emulation/qemu-sbsa.md

@@ -39,4 +39,4 @@ qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <path/to/TFA.fd> \
 
 arm and 9elements worked together in order to create a LBBR compliant bootflow
 consisting of ```TF-A```, ```coreboot```, ```leanefi``` and ```LinuxBoot```. A proof of concept
-can be found here https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-poc
+can be found here <https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-poc>

Documentation/mainboard/ocp/deltalake.md

@@ -32,7 +32,7 @@ in July, 2021.
 ## How to build
 
 OSF code base is publicly available at
-https://github.com/opencomputeproject/OpenSystemFirmware
+<https://github.com/opencomputeproject/OpenSystemFirmware>
 
 Run following commands to build Delta Lake OSF image from scratch:
     git clone https://github.com/opencomputeproject/OpenSystemFirmware.git
@@ -44,10 +44,11 @@ binary blobs. [osf-builder] also provides the top level build system.
 
 Besides coreboot, the Delta Lake OSF solution includes following components:
 - FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
-  is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
-- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
+  is downloaded from <https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg>.
+- Microcode: downloaded from
+	<https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files>.
 - ME ignition binary: downloaded from
-	https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
+	<https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware>
 - ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
 - Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
   U-root as initramfs, is used in the joint development. It is built

Documentation/mainboard/starlabs/byte_adl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel N200 (Alder Lake)
 - EC
     - ITE IT5570E

Documentation/mainboard/starlabs/labtop_cml.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel i7-10710U (Comet Lake)
     - Intel i3-10110U (Comet Lake)
 - EC

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel i7-8550u  (Kaby Lake Refresh)
 - EC
     - ITE IT8987E

Documentation/mainboard/starlabs/lite_adl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel N200 (Alder Lake)
 - EC
     - ITE IT5570E

Documentation/mainboard/starlabs/lite_glk.md

@@ -1,7 +1,7 @@
 # StarLite Mk III
 
 ## Specs
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel N5000 (Gemini Lake)
 - EC
     - ITE IT8987E

Documentation/mainboard/starlabs/lite_glkr.md

@@ -1,7 +1,7 @@
 # StarLite Mk III
 
 ## Specs
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel N5030 (Gemini Lake Refresh)
 - EC
     - Nuvoton NPCE985P/G

Documentation/mainboard/starlabs/starbook_adl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel i7-1260P (Alder Lake)
     - Intel i3-1220P (Alder Lake)
     - Intel i3-1315U (Raptor Lake)

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel i7-1165G7 (Tiger Lake)
     - Intel i3-1110G4 (Tiger Lake)
 - EC

Documentation/mainboard/starlabs/starfighter_rpl.md

@@ -2,7 +2,7 @@
 
 ## Specs
 
-- CPU (full processor specs available at https://ark.intel.com)
+- CPU (full processor specs available at <https://ark.intel.com>)
     - Intel i3-1315U (Raptor Lake)
     - Intel i7-13700H (Raptor Lake)
     - Intel i9-13900H (Raptor Lake)

Documentation/mainboard/system76/gaze15.md

@@ -5,7 +5,7 @@
 - CPU
   - Intel Core i7 10750H
 - EC
-  - ITE5570E running https://github.com/system76/ec
+  - ITE5570E running <https://github.com/system76/ec>
 - Graphics
   - Intel UHD Graphics
   - NVIDIA GeForce GTX 1650/1650 Ti/1660 Ti

Documentation/mainboard/system76/lemp9.md

@@ -6,7 +6,7 @@
     - Intel i7-10510U
     - Intel i5-10210U
 - EC
-    - ITE IT5570E running https://github.com/system76/ec
+    - ITE IT5570E running <https://github.com/system76/ec>
     - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
     - Battery
     - Charger, using AC adapter or USB-C PD

Documentation/mainboard/system76/oryp5.md

@@ -6,7 +6,7 @@
   - Intel Core i7-8750H
   - Intel Core i7-9750H
 - EC
-  - ITE8587E running https://github.com/system76/ec
+  - ITE8587E running <https://github.com/system76/ec>
 - Graphics
   - Intel UHD Graphics 630
   - NVIDIA GeForce RTX 2080/2070/2060

Documentation/mainboard/system76/oryp6.md

@@ -7,7 +7,7 @@
 - Chipset
   - Intel HM470
 - EC
-  - ITE IT5570E running https://github.com/system76/ec
+  - ITE IT5570E running <https://github.com/system76/ec>
 - GPU
   - NVIDIA GeForce RTX 2080 Super (Max-Q)
   - or NVIDIA GeForce RTX 2070 (Max-Q)

Documentation/releases/coreboot-24.02-relnotes.md

@@ -113,7 +113,7 @@ In terms of code size, a QEmu build's ramstage increases
 from 128060 bytes decompressed (64121 bytes after LZMA)
   to 172304 bytes decompressed (82734 bytes after LZMA).
 
-[0] https://github.com/google/wuffs
+[0] <https://github.com/google/wuffs>
 
 
 
@@ -197,7 +197,7 @@ Significant Known and Open Issues
   the version of verstage used in coreboot 24.02.
 
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 
 ### coreboot-wide or architecture-wide issues
 
@@ -282,9 +282,9 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-24.05-relnotes.md

@@ -70,7 +70,7 @@ Additional coreboot changes
 * Numerous fixes for clang support
 * Ongoing code cleanup
 * Docs: Replace Recommonmark with MyST Parser. For changes, see the commit
-  message in https://review.coreboot.org/73158
+  message in <https://review.coreboot.org/73158>
 
 
 
@@ -257,9 +257,9 @@ Significant Known and Open Issues
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Website: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html
+* Main Website: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-24.11-relnotes.md

@@ -83,7 +83,7 @@ Statistics from the 24.08 to the 24.11 release
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 * To be filled in immediately before the release by the release team
 
 
@@ -91,9 +91,9 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html
+* Main Web site: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-4.1-relnotes.md

@@ -31,7 +31,7 @@ months, so the changes between any two release don't become too
 overwhelming.
 
 With the release of coreboot 4.1, you get an announcement (this email),
-a git tag (4.1), and tar archives at http://www.coreboot.org/releases/,
+a git tag (4.1), and tar archives at <http://www.coreboot.org/releases/>,
 for the coreboot sources and the redistributable blobs.
 
 Starting with coreboot 4.1, we will maintain a high level changelog and

Documentation/releases/coreboot-4.10-relnotes.md

@@ -59,7 +59,7 @@ change because doing so breaks other boards.
 
 If you want to use Google Cyan with the release (or if
 you're tracking the master branch), please keep an eye on
-https://review.coreboot.org/c/coreboot/+/34304 where a solution for this
+<https://review.coreboot.org/c/coreboot/+/34304> where a solution for this
 issue is sought.
 
 Deprecations

Documentation/releases/coreboot-4.14-relnotes.md

@@ -147,7 +147,7 @@ or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP
 were unified and optimized:
-* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
+* SKX-SP SoC code is used in [OCP TiogaPass mainboard][3]. Support for
 this board is in Proof Of Concept Status.
 * CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
 this board is in DVT (Design Validation Test) exit equivalent status.
@@ -155,7 +155,7 @@ Features supported, (performance/stability) test scopes, known issues,
 features gaps are described in [4].
 
 
-[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html
-[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html
-[3] ../mainboard/ocp/tiogapass.md
-[4] ../mainboard/ocp/deltalake.md
+[1]: <https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html>
+[2]: <https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html>
+[3]: <../mainboard/ocp/tiogapass.md>
+[4]: <../mainboard/ocp/deltalake.md>

Documentation/releases/coreboot-4.16-relnotes.md

@@ -115,7 +115,7 @@ A few things are lacking in PARALLEL_MP init:
   the BSP CPU.
 - Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
   showed that it's not that hard to do with PARALLEL_MP
-  https://review.coreboot.org/c/coreboot/+/58700
+  <https://review.coreboot.org/c/coreboot/+/58700>
 
 No platforms in the tree have any hardware limitations that would block
 migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.

Documentation/releases/coreboot-4.17-relnotes.md

@@ -239,7 +239,7 @@ Timestamps collected by coreboot can be processed to resemble
 profiler-like output, and thus can be feed to flame graph generation
 tools.
 
-Generating flame graph using https://github.com/brendangregg/FlameGraph:
+Generating flame graph using <https://github.com/brendangregg/FlameGraph>:
 ```
    cbmem -S > trace.txt
    FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg

Documentation/releases/coreboot-4.18-relnotes.md

@@ -78,7 +78,7 @@ vulnerability included in one of the software parts (with the specified
 version) of the firmware.
 
 Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
+<https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/>
 
 - Add Makefile.inc to generate and build coswid tags
 - Add templates for most payloads, coreboot, intel-microcode,

Documentation/releases/coreboot-4.19-relnotes.md

@@ -220,7 +220,7 @@ Statistics from the 4.18 to the 4.19 release
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 ```{eval-rst}
 +-----+-----------------------------------------------------------------+
 | #   | Subject                                                         |

Documentation/releases/coreboot-4.2-relnotes.md

@@ -12,7 +12,7 @@ active as reviewers in that period. Thanks go to all contributors who
 helped shape this release.
 
 As with 4.1, the release tarballs are available at
-http://www.coreboot.org/releases/. There's also a 4.2 tag and branch in
+<http://www.coreboot.org/releases/>. There's also a 4.2 tag and branch in
 the git repository.
 
 This marks the first release that features a changelog comparing it to

Documentation/releases/coreboot-4.20.1-relnotes.md

@@ -62,11 +62,11 @@ This patch supports projects to use _DSM to control USB3 U1/U2
 transition per port.
 
 More details can be found in
-https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
+<https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm->
 
 The ACPI and USB driver of linux kernel need corresponding functions
 to support this feature. Please see
-https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
+<https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm>
 
 
 ### drivers/efi: Add EFI variable store option support
@@ -229,7 +229,7 @@ New authors: ~35
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 ```{eval-rst}
 +-----+-----------------------------------------------------------------+
 | #   | Subject                                                         |

Documentation/releases/coreboot-4.21-relnotes.md

@@ -19,7 +19,7 @@ Historically, the initial branch that was created in a new git
 repository was named ‘master’. In line with many other projects,
 coreboot has decided to switch away from this name and use the name
 ‘main’ instead. You can read about the initial reasoning on the SFC’s
-website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
+website: <https://sfconservancy.org/news/2020/jun/23/gitbranchname/>
 
 At some point before the 4.22 release, coreboot will be switching from
 the master branch to the main branch. This shouldn’t be a difficult
@@ -355,7 +355,7 @@ Significant Known and Open Issues
 ---------------------------------
 
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 ```{eval-rst}
 +-----+-----------------------------------------------------------------+
 | #   | Subject                                                         |
@@ -398,10 +398,10 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Web site: https://www.coreboot.org
-* IRC: https://web.libera.chat/#coreboot
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html
+* Main Web site: <https://www.coreboot.org>
+* IRC: <https://web.libera.chat/#coreboot>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-4.22-relnotes.md

@@ -263,7 +263,7 @@ Statistics from the 4.21 to the 4.22 release
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
 
 ### Payload-specific issues
 
@@ -341,9 +341,9 @@ Plans for the next release
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Website: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html
+* Main Website: <https://www.coreboot.org>
+* Downloads: <https://coreboot.org/downloads.html>
+* Source control: <https://review.coreboot.org>
+* Documentation: <https://doc.coreboot.org>
+* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
+* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-4.3-relnotes.md

@@ -10,7 +10,7 @@ based release schedule. Since the last release, 1030 commits by 114
 authors added a net total of 17500 lines to the source code. Thank you
 to all who contributed!
 
-The release tarballs are available at http://www.coreboot.org/releases/.
+The release tarballs are available at <http://www.coreboot.org/releases/>.
 There's also a 4.3 tag and branch in the git repository.
 
 Besides the usual addition of new mainboards (14) and chipsets

Documentation/releases/coreboot-4.4-relnotes.md

@@ -5,7 +5,7 @@ We are happy to announce the release of coreboot 4.4.  This is our
 fourth quarterly release.  Since the last release, we've had 850 commits
 by 90 authors adding 59000 lines to the codebase.
 
-The release tarballs are available at https://www.coreboot.org/releases/
+The release tarballs are available at <https://www.coreboot.org/releases/>
 There is a 4.4 tag and branch in the git repository.
 
 Log of commit 3141eac900 to commit 588ccaa9a7

Documentation/releases/coreboot-4.5-relnotes.md

@@ -13,7 +13,7 @@ Since the last release in April, the coreboot project has had 1889
 commits by 119 authors.
 
 The release tarballs and gpg signatures are available in the usual place
-at https://www.coreboot.org/downloads
+at <https://www.coreboot.org/downloads>
 
 There is a 4.5 tag in the git repository, and a branch will be created
 as needed.

Documentation/releases/coreboot-4.6-relnotes.md

@@ -8,7 +8,7 @@ The 4.6 release covers commit e74f5eaa to commit db508565
 
 Since the last release in October 2016, the coreboot project had 1708
 commits by 121 authors. The release tarballs and gpg signatures are
-available in the usual place at https://www.coreboot.org/downloads
+available in the usual place at <https://www.coreboot.org/downloads>
 
 There is a pgp signed 4.6 tag in the git repository, and a branch will
 be created as needed.
@@ -22,7 +22,7 @@ Our cbmem debug console was updated with some nice features. The cbmem
 console now persists between reboots and is able to be used on some
 platforms via late init. Also there is a new Linux kernel driver which
 removes the need for the old cbmem tool to read from the cbmem area. You
-can find the patch here https://patchwork.kernel.org/patch/9641997/ and
+can find the patch here <https://patchwork.kernel.org/patch/9641997/> and
 it can be enabled via GOOGLE_MEMCONSOLE_COREBOOT kconfig option in your
 kernel - Note that this name may change going forward.
 
@@ -51,7 +51,7 @@ replacement for the old nvramcui payload. This new payload is called
 cbui and is based on the nuklear graphics library including keyboard and
 mouse support. The cbui payload is currently expected to be merged into
 the main coreboot tree before the next release.  The upstream repository
-is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
+is here: <https://github.com/siro20/coreboot/tree/cbui/payloads/cbui>
 
 ### UEFI support: A long road to go
 
@@ -65,7 +65,7 @@ integrated into the coreboot build. This has several reasons:
 We started to make progress with the integration into our sources and
 the hope is that by the end of the summer, we finally support the edk2
 payload out-of-the- box. See the current patch state at
-http://review.coreboot.org/#/c/15057/
+<http://review.coreboot.org/#/c/15057/>
 
 ### Fighting blobs and proprietary HW components
 
@@ -76,7 +76,7 @@ PSP and microcode. Recently, a way was discovered to let the Intel ME
 run in a functional error state and reduce it from 1.5/5MB to 80KB. It's
 not perfect but it works from Nehalem up to Skylake based Intel systems.
 The tool is now integrated into the coreboot build system. The upstream
-repository is https://github.com/corna/me_cleaner
+repository is <https://github.com/corna/me_cleaner>
 
 Another ongoing improvement is the new utility blobtool. It is currently
 used for generating the flash descriptor and GbE configuration data on

Documentation/releases/coreboot-4.8.1-relnotes.md

@@ -63,7 +63,7 @@ Fixed Bugs
 * qemu-i440fx: Fix ACPI checksum corruption
 * intelmetool: Fix crash, support ME11+ platforms, fix bootguard
 detection
-* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 (https://github.com/nccgroup/TPMGenie)
+* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 ()<https://github.com/nccgroup/TPMGenie>)
 * asrock/b75pro3-m: Fixed HDMI
 * Intel/ibexpeak: Fix missing ACPI PIRQ entries
 * Intel/nehalem: Fix freeze during chipset lockdown
@@ -86,7 +86,7 @@ Intelmetool
 Documentation
 -------------
 * Switch from Hugo to Sphinx for the Documentation
-* Working on markdown documentation for https://doc.coreboot.org
+* Working on markdown documentation for <https://doc.coreboot.org>
 
 Added 17 mainboards
 -------------------

Documentation/soc/intel/xeon_sp/community_preview_guide.md

@@ -4,10 +4,10 @@ Xeon Scalable Processor coreboot Community Preview Guide
 ## Background
 
 Xeon 6 basic boot supports are initially upstreamed at
-https://review.coreboot.org/q/topic:%22Xeon6-Basic-Boot%22.
+<https://review.coreboot.org/q/topic:%22Xeon6-Basic-Boot%22>.
 
 Full feature supports are previewed at
-https://review.coreboot.org/admin/repos/intel-dev-pub,general
+<https://review.coreboot.org/admin/repos/intel-dev-pub,general>
 
 The supported platform status are as below,
 

Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md

@@ -136,8 +136,8 @@ second phase covers the assembly of the final image.
 By having a global picture of the final image’s requirements, we can also
 avoid issues where files added earlier may prevent later additions that have
 stricter constraints - without resorting to hacks like
-https://chromium-review.googlesource.com/289491 that reorder the file addition
-manually.
+<https://chromium-review.googlesource.com/289491> that reorder the file
+addition manually.
 
 Example
 -------

Documentation/technotes/console.md

@@ -1,7 +1,7 @@
 # coreboot Console
 
 coreboot supports multiple ways to access its console.
-https://www.coreboot.org/Console_and_outputs
+<https://www.coreboot.org/Console_and_outputs>
 
 
 ## SMBus Console