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mb/google/brya/var/marasov: Enable GPP_F9 GPIO for early panel power-on

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This change enables the GPP_F9 GPIO, which controls the SLP_S0_GATE_R
signal and subsequently the SYS_SLP_S0IX_L signal.

By enabling GPP_F9 early in the boot process, we ensure the panel is
powered on correctly and able to render the eSOL message.

BUG=b:372737590
TEST=Verified panel power-on by observing eSOL during build on
google/marasov.

Change-Id: I727a72d9583575b2bbebe2c3b75c980170dd36b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Subrata Banik 2024-12-13 01:40:44 +05:30
commit 46df9e1d38
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/google/brya/variants/marasov/gpio.c
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@ -2,6 +2,7 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <intelblocks/early_graphics.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
@ -222,6 +223,17 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_D2, 0, DEEP),
};
static const struct pad_config early_graphics_gpio_table[] = {
/* F9 : BOOTMPC ==> SLP_S0_GATE_R */
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
};
const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_graphics_gpio_table);
return early_graphics_gpio_table;
}
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);