Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers,
each with a different number of EINT bits. In preparation for the
upcoming MT8196 EINT unmasking support, replace the `eint_event_reg`
struct (which has a hardcoded register number) with an array
`eint_event` to specify the EINT base register(s).
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load MCUPM firmware and boot up MCUPM in ramstage.
It takes 54 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308
mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes)
TEST=Build pass and we can see the mcupm logs after reset releases.
BUG=b:317009620
Change-Id: I223f245d384f32d54f6170a28b29573638f77296
Signed-off-by: Agogo Huang <agogo.huang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
mt6373_init_pmif_arb() needs to be initialized for SD card to control
the regulator.
TEST=emrege-rauru coreboot
TEST=The assertion is gone on Rauru during normal boot.
Change-Id: I7e3265bb62a6c78d44e2c756be9a020a49a03056
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85969
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return to the caller immediately if pmif_arb has been initiailized. In
this way, we can skip unnecessary check and reduce the access to the
PMIF register.
TEST=emerge-geralt coreboot && emerge-rauru coreboot
Change-Id: Id1d11f8b238855edb393d77151159792e7716d22
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The function rtc_get_frequency_meter() already uses the wait_us() macro,
so the stopwatch variable "sw" is not needed.
Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses new RC mode with clk_buf driver, and needs srclken_rc to
send PMRC_EN. PMRC_EN will collect the requirements of all users,
such as MD, GPS, PCIE, NFC.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85842
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses MT6685 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on. RC mode will determine which clocks to be
turned on based on users' requests, which is collected into PMRC_EN
register by srclken_rc.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
With CB:85918 and CB:85930, we can clean up the TODO in mtk_dp_mask.
Follow DP Phy APIs to use `assert` for the param examination.
TEST=verified on Ciri and Navi
Change-Id: I94e6ad36d190d773876cbb43eb4ebe17164f3c92
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85931
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8196's eDP architecture is different from previous SoCs. DP Phy needs
to be configured during the initialization. Add read/write APIs for DP
Phy register configuration. Add a mock definition EDP_PHY_BASE for the
SoC that do not support DP Phy configuration.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-rauru coreboot
TEST=check FW screen on Navi
Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85914
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the functions that can be shared with MT8196 to dptx_hal_common.c.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
TEST=verify FW screen on Navi
Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add common definitions and `mainboard_get_storage_type` API for
determining the storage type from mainboard.
TEST=emerge-rauru coreboot
Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85878
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the functions that can be shared with MT8196 to dptx_common.c.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85860
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add `_common` postfix to the header files located in
common/dp/include/soc/. The patch helps MT8196 managing its own DP
register difition and macros in its include/soc folder.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Correct the argument type of the mt6363_sdmadc_read API and the return
value type of the mt6363_read16 API.
TEST=Build pass
BUG=b:317009620
Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The MT6363 buck5 API's mask and shift settings are incorrect, preventing
the buck from being disabled. Resolve the issue by correcting these two
values.
BUG=b:365445188
TEST=build pass, check buck5 is power off after calling the
mt6363_enable_buck5 API.
Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85838
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The initialization process of SPMI requires a certain amount of time
(0.5ms) to ensure all components are correctly configured and
synchronized. Otherwise, if the SPMI calibration fails, it will result
in the non-serial firmware failing to boot.
TEST=Build pass, non-serial firmware boot ok.
BUG=b:341054056
Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
GPUEB is a micro-processor used for GPU power management. It is also
responsible for controlling GPU DVFS and GPU thermal throttling. This
gpueb load flow adds 47ms to the boot time.
coreboot log:
CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374
Loaded (and reset) gpueb_fw.img in 47 msecs.
TEST=Boot ok
BUG=b:317009620
Signed-off-by: Andy.Hsu <andy.hsu@mediatek.corp-partner.google.com>
Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current Pull-Down capabilities of the SPMI are insufficient and
require optimization. Configure the SCL and SDA of the SPMI-P to
Pull-Down mode on MT8196 SoC side. It is done only once during the SPMI
read check to fix SPMI clock calibration failure.
TEST=Build pass
BUG=b:361174333
Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85751
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In MT8196, CKSYS achieves power efficiency by dynamically turning the
clocks on or off based on the status provided by PERI.
TEST=Build pass, boot log:
mtk_cksys_init = 0x1
BUG=b:317009620
Change-Id: I70f710f068d7d882037691930a90c83adaab15d2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add MT6685 initial settings and ADC init settings to support Thermal
Information Acquisition (TIA). TIA will read thermal info in HW.
TEST=Build pass
BUG=b:317009620
Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85734
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The MFGPLL_*_BASE addresses are based on MFGSYS_BASE (0x40000000)
instead of IO_PHYS (0x10000000). Rewrite the address calculation for
readability.
Also rename these macros to MFG_PLL_* to make them consistent with other
macros to be added in CB:85654.
Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85740
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces this file to
"GPL-2.0-only OR MIT" license for better code re-use in other open
source software stack.
BUG=b:379008996
BRANCH=none
TEST=build pass
Change-Id: I2821a8c097b8d22e1aa91b316ae0fdce80f342de
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85723
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add watchdog support for MT8189.
BUG=b:379008996
BRANCH=none
TEST=build pass and WDT makes DUT reboot when MTK_WDT_MODE_ENABLE is
set.
Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85678
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting from MT8196, MediaTek platform introudces a new blob named
MediaTek firmware support package (mtk-fsp). The features of mtk-fsp
include but not limit to,
- Security settings, e.g: Device Access Proctection Control, Security
Memory Protection Unit.
- Initialization for advanced CPU frequency control.
This patch implements APIs for
1) Exchanging data between coreboot and mtk-fsp.
2) Loading and running the mtk-fsp blob at a specific bootstage.
BUG=b:373797027
TEST=emerge-rauru coreboot; Run mock blob and return from mock blob.
Change-Id: Idef3518f9763fe5f74adb459c137db164563e483
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85665
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update timer macro name for common.
The new ICs (e.g. mt8196, mt8189) will no longer use GPT. In order
to improve code readability, replace GPT_MHZ with TIMER_MHZ for
existing SoCs.
BUG=b:379008996
BRANCH=none
TEST=Build pass, Macro name is correct.
Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4
Signed-off-by: Ke Zheng <ot_ke.zheng@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85681
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM
and fix the SPM register definitions. SPM needs its own firmware to
enable SPM suspend/resume function which turns off several resources
such as DRAM/mainpll/26M clk when linux system suspends.
coreboot log:
CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c
mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt)
TEST=build pass
BUG=348147674
Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85599
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new folder and basic drivers for Mediatek SoC 'MT8189'.
Also enable UART and ARM arch timer.
This commit includes the necessary initialization files for MT8189,
which cannot be shared with other existing SoCs.
The modules included are:
- Memory layout: MT8189 has only 64KB of SRAM, differing in space
allocation compared to other SoCs.
- PLL: Different SoCs have different PLL designs. In this commit,
we provide the most basic settings, with more configurations to
be added in future commits.
- Timer: MT8189 uses timer v2, unlike other SoCs which use timer v1.
- SPI: The SPI driver for different SoCs varies depending on the GPIO/
PIN MUX used. In this commit, we provide the most basic settings,
with more configurations to be added in future commits.
- EMI: MT8189 uses common EMI code along with MT8189-specific
'dram_parameter.h'. This commit provides an EMI stub to ensure
coreboot builds successfully. Future DRAM-related commits will
utilize the common EMI code.
BUG=b:379008996
BRANCH=none
TEST=saw the coreboot uart log to bootblock
Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85616
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek pwrsel (Power Select) is mainly used to reduce power
consumption, controlled by mcupm.
BUG=b:317009620
TEST=Build pass
Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8196's SPM_SYSTEM_BASE_OFFSET has a different offset due to the
hardware design. To avoid adding a new kconfig for differentiation,
migrate this definition into SoC specific value.
BUG=none
TEST=emerge-geralt coreboot && emerge-corsola coreboot
Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85625
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The init flow in `spm_init_pcm_register` and `spm_kick_pcm_to_run` is
simplified on MT8196. And MT8196 does not have corresponded registers
used by these two functions. Therefore, move these two function to a
separated file and simply name it as spm_v1.c.
BUG=none
TEST=emerge-geralt coreboot && emerge-corsola coreboot
Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85623
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rauru reference design has SD card interfaces, so we have to configure
it in ramstage.
Implement msdc.c (memory and SD Card controller) to place the SD card
drivers.
This implementation is based on chapter 10.3 in MT8196 Functional
Specification.
TEST=Build pass
BUG=b:317009620
Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85564
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug.
Rename VLPCFG_BASE to VLP_CFG_BASE.
TEST=Build pass, When we encounter a bus hang and HW watchdog triggers
a reset to the platform, the tracker will print the
latched information:
[INFO ] **Dump %s aw debug register start**
[INFO ] xxxxxx, 0x1c600000, 0x0, 63
This means that the 63rd entry latch accessing 0x1c600000 has a bus
timeout.
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84929
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMinfra is the Multimedia Infrastructure. All the Multimedia modules
depend on it. This file adds some initial settings for MMinfra.
Test=Build pass
BUG=b:317009620
Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.corp-partner.google.com>
Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to its
SRAM space and then enable it.
It takes 20 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314
mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes)
TEST=can see the sspm logs.
BUG=b:372173976
Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0
Signed-off-by: Kenji Yu <kenji.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
