soc/mediatek/common/dp: Add read/write APIs for DP Phy register

MT8196's eDP architecture is different from previous SoCs. DP Phy needs
to be configured during the initialization. Add read/write APIs for DP
Phy register configuration. Add a mock definition EDP_PHY_BASE for the
SoC that do not support DP Phy configuration.

BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-rauru coreboot
TEST=check FW screen on Navi

Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85914
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/dp/dptx_common.c

@@ -215,6 +215,7 @@ static void dptx_fec_ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel)
 void dptx_init_variable(struct mtk_dp *mtk_dp)
 {
 	mtk_dp->regs = (void *)EDP_BASE;
+	mtk_dp->phy_regs = (void *)EDP_PHY_BASE;
 	mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3;
 	mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2;
 	mtk_dp->train_info.linklane_count = DP_LANECOUNT_4;

src/soc/mediatek/common/dp/dptx_hal_common.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <delay.h>
@@ -66,6 +67,37 @@ void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask)
 	mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0);
 }
 
+u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset)
+{
+	void *addr = mtk_dp->phy_regs + offset;
+
+	assert(mtk_dp->phy_regs);
+	assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT);
+
+	return read32(addr);
+}
+
+void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
+{
+	void *addr = mtk_dp->phy_regs + offset;
+
+	assert(mtk_dp->phy_regs);
+	assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT);
+
+	write32(addr, val);
+}
+
+void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask)
+{
+	void *addr = mtk_dp->phy_regs + offset;
+
+	assert(mtk_dp->phy_regs);
+	assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT);
+	assert((val & mask) == val);
+
+	clrsetbits32(addr, mask, val);
+}
+
 void dptx_hal_verify_clock(struct mtk_dp *mtk_dp)
 {
 	u32 m, n, ls_clk, pix_clk;

src/soc/mediatek/common/dp/include/soc/dptx_common.h

@@ -198,6 +198,7 @@ struct mtk_dp {
 	u32 max_hdisplay;
 	u32 max_vdisplay;
 	void *regs;
+	void *phy_regs;
 	int disp_status;
 	bool power_on;
 	bool audio_enable;

src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h

@@ -65,6 +65,9 @@ bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
 bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
 				   int swing_value, int preemphasis);
 u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp);
+u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset);
+void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
+void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
 u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset);
 void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask);
 void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);

src/soc/mediatek/mt8188/include/soc/dptx.h

@@ -5,4 +5,6 @@
 
 #include <soc/dptx_common.h>
 
+#define EDP_PHY_BASE	0
+
 #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ */

src/soc/mediatek/mt8195/include/soc/dptx.h

@@ -5,4 +5,6 @@
 
 #include <soc/dptx_common.h>
 
+#define EDP_PHY_BASE	0
+
 #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ */